27.5 A 1.6GB/s DDR2 128Mb Chain FeRAM with Scalable Octal Bitline and Sensing Schemes
3:45 PM
H. Shiga, D. Takashima, S. Shiratake, K. Hoya, T. Miyakawa, R. Ogiwara, R. Fukuda, R. Takizawa, K. Hatsuda, F. Matsuoka, Y. Nagadomi, D. Hashimoto, H. Nishimura, T. Hioka, S. M. Doumae, S. Shimizu, M. Kawano, T. Taguchi, Y. Watanabe, S. Fujii, T. Ozaki, H. Kanaya, Y. Kumura, Y. Shimojo, Y. Yamada, Y. Minami, S. Shuto, K. Yamakawa, S. Yamazaki, I. Kunishima, T. Hamamoto, A. Nitayama, T. Furuyama
Toshiba Semiconductor, Yokohama, Japan
A 1.6GB/s nonvolatile 128Mb chain FeRAM in 0.13µm CMOS is demonstrated. The 87.7mm2 die uses 0.252µm2 cell with a cell sensing signal of 200mV, an octal bitline architecture, low-parasitic-capacitance sensing, and dual-metal platelines. Power-supply bounce due to the 400MHz clock is suppressed to 50mV by event-driven current suppliers.
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