Brian, ALL, good news about K6+:
From Rick Gideon, Jr. publisher of the new betterchips.com site (formerly AMD/K6 Appreciation Center) comes this:
...I have some interesting news on the K6+ series. ÿAs was previously believed, the K6+ series would have a pipe-lined FPU, this is WRONG. The FPU will NOT be pipelined, HOWEVER, this FPU will have pipelined instructions; Apparently, the MMX2 instruction sets are pipelined to pipeline all instructions entering the FPU. Thus, the FPU, non-pipelined, will perform as a pipelined FPU. Yes, the K6+ will operated FPU instrutions 4-8 sets per clock cycle. So don't worry about the FPU, it will be more powerful than anyother desktop chip available today. Have more later.
I think he's a little confused about the details, but even if the K6+ could only do 2 floating point ops per clock cycle, it would be twice as powerful as the hyped Intel FPU.
AMD has figured out a way to start and complete multiple floating point operations in a single clock cycle. This is much better than Intel, which can only start one op each cycle and takes five cycles to complete it.
BTW, put the reference above in your bookmarks
Petz |
