AMD:News, Press Releases and Information Only! Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : AMD:News, Press Releases and Information Only!

AMD 216.00

-0.7%

Dec 4 3:59 PM EST

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Petz who wrote (1681)	10/24/1997 7:31:00 PM
From: Yousef	Read Replies (1) of 6843

John, Re: "Chips are built in layers of silicon ... K6 there are 5 layers ... light controls where transistors and resistors are located ... by moving the L1 cache, it may be possible to shorten critical distances on the chip and speed it up." John, you are in "way over your head" on this one. There are 19 mask layers in a .25um process (the one I am familar with). I could go through a typical process flow and describe each mask layer if you/or others are interested. Each mask layer requires going through an exposure tool that uses light (365nm -> 248nm) to transfer an image from the mask to a photosensitive material spun on the wafer called photoresist. This material after patterning then acts as an etch block (or implant block) for subsequent process operations. The mask placement relative to the wafer is what determines where the FET's are placed ... not the light. To move the cache, probably all mask layers (all 19) need to be changed. To improve speed, typically 1 -> 3 mask layers will be re-done to fix one speed path. Hope this helps. Make It So, Yousef

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next