This Year, Entire Roadmap Changes
The ITRS Roadmap will see a new edition go on-line in December. To get ready, participants met in San Francisco for the ITRS Summer Public Conference held Wednesday during SEMICON West. New materials and devices are being readied to extend CMOS and to ready the industry for the day when charge-based devices run out of steam.
Dave Lammers, News Editor -- Semiconductor International, 7/16/2009
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About 140 technologists attended the day-long ITRS meeting, most of them participants in the 16 technology working groups (TWGs) that form the ITRS. Unlike last year, the 2009 edition will include major revisions; it will be posted to the ITRS Web site (www.itrs.net) in December.
*** Paolo Gargini, the ITRS chairman since 1998, said in recent years performance gains have come less from brute transistor scaling and more from materials innovations, such as strained silicon, high-k/metal gates and others. "The big picture is that shrinking is not the only knob we have been turning," Gargini said, adding that packaging and 3-D interconnects are seeing major innovations that will be reflected in the 2009 edition's chapters on packaging and interconnects.
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New Materials Gaining Momentum
Jim Hutchby, chairman, ITRS Emerging Devices TWG
Jim Hutchby, chairman of the ITRS emerging devices TWG, said the pace of materials and device innovation is picking up. "Carbon-based nanoelectronics are making rapid progress. They can be first applied to FETs, and then are likely to branch out to other areas," said Hutchby, a program manager at the Semiconductor Research Corp. (SRC).
Carbon nanotubes (CNTs), graphene nanoribbons and ferroelectric materials in the gate, are among the new materials being studied for logic applications. Memories also are making dramatic shifts, with spin-torque MRAMs, phase-change RAMs, nanoionic memories and several versions of resistive memories among the memory candidates being researched.
Hutchby said the next year will involve an intense effort to select the emerging device types that deserve serious R&D study and funding. The emerging devices TWG and the emerging materials TWG will work together on the selection recommendations, reporting their findings by May 2010. "We need to figure out which are worthy," Hutchby said.
Jeff Welser, director of the Nanoelectronics Research Initiative (NRI) agreed that graphene-based devices have long-term promise, with about half of the NRI's post-CMOS device research projects involving some form of graphene. However, getting to low defect levels for mass-produced graphene layers represents a major challenge, Welser said.
Michael Garner, head of the emerging materials TWG, warned that some of the emerging materials present thorny toxicity challenges "which are stimulating research in ES&H."
Nevertheless, Garner said many new materials are likely to come into the semiconductor industry, including nanotubes on quartz, nanowires, germanium and III-V channels, as well as ferroelectric and chalcogenide memories. A slew of complex metal oxides are receiving intense attention.
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Garner, who manages Intel's external materials research strategy, said academicians have developed innovative R&D-level resist materials, including tethered anthracene, dendrimers, molecular glasses and others. He also said the emerging materials TWG is closely studying include self-assembling materials.
Alan Allan, International Roadmap Committee
Alan Allan, an Intel technology strategy manager, reported on the overall roadmap characteristics. "This is the year everything changes. The last three years we have made adjustments, but this year all the modules will change."
The two-year cycle for density doubling on microprocessors is likely to continue until 2013, but then may slow down to a three-year cycle, Allan said. NAND flash has been on an aggressive cadence, but the four-bits-per-cell technology is likely to be delayed until 2012, he said, adding that three-bits-per-cell will serve in the interim.
"The number of transistors on MPUs are expected to cross the DRAM bits per chip," Allan said, as MPUs move to ~two billion transistors while DRAMs hit the 2 Gbit density.
The DRAM chip size is likely to shrink, as DRAM makers manage 4F2 designs (a bit cell size that is four times larger than the smallest lithographic feature), down from the 6F2 possible now. While DRAMs are likely to shrink, the average chip size for the NAND flash chip is likely to grow as densities skyrocket, he added.
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Kwok Ng, head of the process integration, devices and structures (PIDS) TWG, said the 2009 ITRS will include new metrics on how basic logic performance is measured, including updated standards for pFET performance, ring oscillators and others. Power consumption will be measured against a standard Ioff of 100 nanoAmperes per micron, he said.
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