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Politics : RAMTRONIAN's Cache Inn

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To: NightOwl who wrote (14413)	8/22/2009 4:33:08 PM
From: NightOwl	Read Replies (1) of 14464

Well I believe I have found a reference to the type of "3D NAND" device that Toshiba and Sandisk are working on. Its some sort of "verticle" structure in which the charge traps for storage are mounted within a verticle channel, see p.21: lsi.t.u-tokyo.ac.jp What isn't clear from the slides above is why it would be cheaper than FeNAND... it may be because it gets multiple bits within each verticle channel... or why it won't suffer from NAND's scaling difficulties around the 20-10nm process nodes. There is a criptic reference to "relaxed" design rules which leads me to think they simply plan on avoiding true sub 20nm process nodes by stacking multiple bits/charge traps. But why that structure would allow greater endurance or reliability than standard NAND I don't know. In any case one thing is clear. It would be insanely difficult to use their design for true L1, embedded memory. I suspect it only makes sense at all because it is cheap and provides "good enough" performance for the broadest base of consumer driven apps. Or at least Toshiba/Sandisk think the performance will be "good enough" to do so. That leaves high end storage class devices and low power mobile/embedded applications for other IP to compete for. 0\|0

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