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Technology Stocks : Altera
ALTR 53.61+1.3%Jul 7 5:00 PM EST
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To: Bill Martin who wrote (1364)11/1/1997 8:52:00 PM
From: Bilow  Read Replies (1) of 2389
 
It was my understanding that the Altera FPGA conversion, as well
as the Xilinx conversion, consisted of replacing the RAM cells
with ties to VSS or VCC. Thus you did save space, but logic was
still implemented as multiplexors.

I should explain: These FPGAs use multiplexors to provide logic
functions. A 16 to 1 multiplexor is wired up with 16 ram cells at
the input. These ram cells define an arbitrary function of four
variables. The four multiplexor address lines are where you provide
the function input. When they convert to FPGA, the ram cells are
tied high or low, but the logic is still implemented by feeding the
four inputs to address inputs. Consequently, a 4-input NAND
gate uses as much space as a 4-input XOR gate, rather than
much less as a full ASIC would use.

This design technique means that they can implement it as a sea
of gates sort of thing. That way they can share process steps
between different designs. I.e, only the metalization layers differ.
It also has the advantage that when your original design was
done by a hone-head engineer who didn't design a synchronous
system, you don't end up messing with the relative time delays as
much as a conversion to a full custom. This reduces the
probability of bringing an incipient race condition to life.

If someone knows better, please correct me, I haven't turned
an FPGA into the "hard-wired" version in about 3 years.

-- Carl
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