SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Paul Engel who wrote (25605)11/7/1997 12:50:00 AM
From: Petz  Read Replies (3) of 1578938
 
Paul, thanks for Robert Colwell's presentation at the Microprocessor Forum. One thing he pointed out about Slot 1 is that Intel does purchase the "commodity SRAM" for the L2 cache. I believe I saw a posting on the Intel thread that this costs Intel $20, more or less depending on the processor speed.

If you figure there's 25000 mm sq useable area on an 8" wafer costing (roughtly) $2200 (including chemicals, labor, etc), then putting the L2 cache directly on-chip makes sense if its less than 1/110th the size of the wafer, or 227 mm sq. Of course, if only 50% of the processors are good, you'd need to fit it in 114 mm of space. This still seems like a pretty big area in which to fit 512K SRAM.

With $20 SRAM savings and additional mechanical costs eliminated, I can see why Intel wants to eliminate the L2 cache from the module, but its equally clear that the long term low cost solution is on-chip L2 cache as announced by AMD for K6-3D in 2Q '98.

Petz
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext