Trio forms 3-D chip alliance
Mark LaPedus
(06/21/2010 10:15 AM EDT)
URL: eetimes.com
SAN JOSE, Calif. -- Elpida Memory Inc., Powertech Technology Inc. and United Microelectronics Corp. (UMC) have formed an alliance to speed up the development of three-dimensional (3-D) chips at the 28-nm node as well as other processes.
The 3-D devices will be based on through-silicon-vias (TSVs). This collaboration will leverage the strengths of Elpida's DRAM technology, Powertech's assembly, and UMC's foundry logic technologies to develop 3-D devices. This includes devices that integrate logic and DRAM.
It's unclear which company will actually make the 3-D devices. The companies also did not announce a timetable.
A plethora of companies, including ASE, Elpida, IBM, Intel, Samsung, Toshiba, TSMC and others, are exploring the possibly of stacking current devices in a 3-D configuration.
Experts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying TSVs. The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.
So far, chip makers are shipping limited 3-D devices based on TSVs, mainly CMOS image sensors, MEMS, and, to some degree, power amplifiers. Elpida claims to have devised a DRAM based on TSVs.
There are several problems with TSV technology: Lack of EDA design tools; complexity of designs; integration of assembly and test; cost; and lack of standards.
But close integration of DRAM and logic technologies using TSV technology are expected to deliver the performance for a new class of chips. The UMC/Powertech/Elpida collaboration will facilitate the development of a total solution that includes logic/DRAM interface design, TSV formation, wafer thinning, testing and chip stacking assembly for customers.
"Last year Elpida was the first to successfully develop an 8-gigabit DRAM based on TSV technology," said Takao Adachi, director and chief technology officer of Japan's Elpida Memory, in a statement.
"The big advantage of this technology is that it enables a large number of I/O connections between logic and DRAM devices. This can massively increase the data transfer rate and reduce power consumption, making possible completely new kinds of high-performance devices,'' he said.
''However, we need a solid partnership with a logic foundry to make this happen. The joint development that we now plan with UMC means that we can use the most advanced TSV integration technology to bring together our advanced DRAM technology and UMC's leading-edge logic foundry technology including experience in providing SoC solutions such as advanced microprocessors,'' he said. ''Our plan now is to speed up development in a way that supports ultimate system solutions that will be made possible by freely joining together all kinds of devices through TSV integration." |
