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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 231.83+1.7%Jan 16 9:30 AM EST

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To: combjelly who wrote (264500)9/2/2010 8:01:54 AM
From: mas_Read Replies (1) of 275872
 
"So it isn't like the process is busted."

TSMC reckon gate-first HKMG is a technical non-flyer

maltiel-consulting.com

Last summer, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) made a surprising decision to use a gate-last deposition method for the high-k/metal gate stack of its 28 nm transistors. TSMC's decision to use a replacement metal gate (RMG) technique was guided by history, said S.Y. Chiang, the senior vice president at TSMC in charge of R&D.

Two decades ago, the semiconductor industry went through a similar tussle, when early CMOS developers tried to use an N+ poly gate for both the N-channel and P-channel devices. "When the industry began to do PMOS, companies found an N+ poly gate doesn't work well," Chiang said. "It was difficult to lower the Vt, so some people tried to add a counter dopant into the active region of the silicon channel to try to match the Vt. That caused a lot of problems, and made gate control and SCE (short channel effects) much worse."

The gate-first approach to high-k ran into similar Vt control problems, Chiang said. Efforts to use capping layers improved gate-first performance, but a gate-first cap-layer process "gets very, very complicated and difficult to do," he said. Two decades ago, for one technology generation, companies also tried to adjust the Vt for both NMOS and PMOS. "We went through exactly the same step when in our history we tried to use N+ poly," Chiang said.

Asked about the restrictive design rules (RDRs) required for the gate-last method, Chiang said TSMC has been working with the layout teams at its largest customers to adjust to the gate-last high-k flow.

"With the gate-last technology, we do have some restrictions," he said. "There is difficulty in planarizing it. However, if the layout team is willing to change to a new layout style, then they can get a layout density that is as good as with the gate-first approach. Not better, but the same. And it is not that difficult." With high-k, Chiang added, "everybody — the process people as well as the layout people — need to adjust the way they do things in order to make the products competitive."
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