jtj and others, Here's a more detailed version of IBM's plan:
techweb.cmp.com
IBM plans state-of-the-art 300-mm faciity
By Ashok Bindra
FISHKILL, N.Y. -- IBM Microelectronics has disclosed its plan to build a state-of-the-art 300-mm (12-inch) wafer pilot facility here for future gigabit DRAMs, 64-bit microprocessors and systems-on-a-chip.
The center will be based on guidelines generated by the 13-member International Consortium I300I, a wholly owned subsidiary of Sematech (Austin, Texas). IBM has earmarked $700 million as its investment in the development of this pilot line.
The fully automated facility also signals the move toward copper interconnects and X-ray lithography, both technologies pioneered by IBM researchers. In fact, using copper interconnects in lieu of traditional aluminum interconnects for speed and density was unveiled recently by IBM researchers. According to IBM, the X-ray lithography equipment is also being modified to accommodate 300-mm wafers.
To enable the semiconductor industry to convert to 300-mm wafers efficiently and smoothly, IBM is developing its new facility on the guidelines established by the International 300-mm Initiative (I300I). The 13-member I300I includes three semiconductor companies from Europe, three from Korea, one from Taiwan and six from the United States. The 300-mm transition is gaining momentum, as multi-company consortia in the United States and Japan push for this conversion, stated the standards-setting organization SEMI (Mountain View, Calif.).
By the time IBM's pilot facility is up and running, other major international semiconductor suppliers are projected to migrate to 300-mm lines. Global semiconductor makers in Japan are planning to ready prototype 300-mm lines by the end of 1998, with some production forecasted for late 1999.
IBM is putting all its capabilities together to become a powerful semiconductor company, said Handel Jones, president of market-research firm International Business Strategies (Los Gatos, Calif.). "We see it as a continuation of its efforts to become a technology leader in the merchant market," noted Jones.
The early move toward larger wafer size will allow IBM to participate in high-volume chips of the future, Jones said. Plus, combining larger wafers with finer geometries and better interconnects will enable IBM to produce faster chips with lower power consumption and cost to compete effectively in portable electronics, he added.
Similar opinion was also expressed by Fred Zieber, a market analyst from Pathfinder Research Inc. (San Jose, Calif.). With this move, IBM is pushing the state-of-the-art at every layer of the chip, Zieber said.
While the initial gigabit DRAMs will implement 0.18-micron design rules, IBM intends to shift quickly to 0.15-micron feature sizes, although the timetable for this shift was not available.
According to IBM, its development team has demonstrated the capability of using X-ray lithography to build future chips with circuit features of 0.15 microns and below. Furthermore, IBM said that X-ray technology appears to be the most promising post-optical lithography. Jones cautioned that X-ray has yet to be proven in high-volume production. "This is a major challenge," Jones said.
Over time, IBM also intends to develop silicon (SiGe) germanium chips at this center. On the drawing board are RF front ends and low-noise amplifiers (LNAs). Experts believe that larger wafer size will enable IBM to reduce the cost of SiGe chips, which has been a major hurdle, even though the technology can provide much faster devices with lower power consumption.
Slated to become operational by early1999, the new development facility it is expected to be producing chips only toward the end of 1999. Volume production is planned for 2001, according to a source at IBM. |
