Lamar - Re: "..a higher speed interface superimposed on a DRAM
core, "
This is not quite true.
Although the DRAM cell and sense amps and decode circuitry are basically the same, the internal organization of Rambus RDRAM device is quite a bit different.
Internally, the DRAM is organized as 1, 2 or 4 (or more) blocks of memory, each 2 MegaBytes (16 MegaBits) in size. Each block has a 2,048 sense amps for reading one row of 2,048 bits (a page) at once. These 2,048 bits x n blocks (n = 1,2,4..) are then funneled into 8 (or 9) bits for external read/write operations to the system host memory controller.
These sense amps then act as a fast block of cache memory for read operations.
Further, the RDRAM has a register structure which is written to by the host controller, using a transaction process, not unlike the transaction process of the Pentium Pro/Pentium II I/O busses.
These registers are written to by the system memory controller to set up the RDRAM for the various types of data read/write operations.
In sequential block mode, a system can read out 8 bits at 1.67 nS intervals (for current technology - this will decrease as technology advances occur) continuously for sequential reads where the data are in the groups of 2,048 sense amp "cache" blocks. The number of these blocks increases as more RDRAM memory chips are added to the system - effectively expanding block sizes without widening the memory bus.
Misses to the current page result in a time penalty (latency) until the appropriate new row can be loaded into the sense amps. The RDRAM signals to the host controller that a page miss has occurred, and the controller can then access a different block within a memory chip, or a different memory chip in the system entirely while the initial page miss is resolved.
This keeps the memory system busy, minimizing the effects of these page misses. Random access (non-sequential) memory accesses are also handled in such a way to minimize overall system latency by virtue of the communication beteween the RDRAM chips and the host controller.
Power consumption is reduced since the RDRAM chips that do not contain the data currently being accesses enter a standby power mode, effectivelly keeping only the one chip with the appropriate data active to complete the data read operation.
The electrical interface is also well specified, allowing for low voltage swings ( a signal reference voltage of 2.5 volts is recommended) which help enable the higher speed buss. And, the layout of the busses is also well definced by RAMBUS, including terminations to minimize transmission line effects.
As for complexity, the RAMBUS DRAMS in a Nintendo 64 are so "simple" that the N64 is made with a simple 2-sided PC board - incredibly simple and low cost.
Paul |
