Xilinx Delivers First Public Access Release of its Next-Generation Vivado Design
Suite
Accelerates time to implementation from C and RTL up to 4x and improves
performance up to 15 percent
SAN JOSE, Calif., July 26, 2012 /PRNewswire via COMTEX/ -- Xilinx, Inc. (XLNX)
today announced it has made available its first public release of its
next-generation design environment. The Vivado(TM) Design Suite 2012.2 is now
available at no additional cost to all ISE? Design Suite customers who are
currently in warranty. This release is the first in a two-phase rollout, with the
first phase focused on accelerating time to implementation from C and RTL, and
the second focused on accelerating time to integration of system-level functions.
Vivado Design Suite 2012.2 delivers a highly Integrated Design Environment (IDE)
with a completely new generation of system-to-IC tools that include High-Level
Synthesis, RTL Synthesis with the industry's best SystemVerilog support,
revolutionary analytical place and route, and an advanced SDC-based timing engine
so developers can increase their productivity with a 4x acceleration in design
implementation.
Vivado Design Suite Accelerates Implementation from RTLGiven the size and
complexity of today's designs, developers face multidimensional design challenges
that prevent them from achieving automated design closure. The Vivado Design
Suite 2012.2 place and route technology accelerates implementation cycles by
using analytical techniques to optimize for multiple and concurrent design
metrics, such as congestion, total wire length and timing. For complex designs,
this results in performance improvements of 15 percent corresponding to a 1 speed
grade advantage over the ISE Design Suite. The same performance improvement also
extends Xilinx's high-performance leadership over competing devices by 3 speed
grades among the mid-range families, while delivering better performance vs.
power trade-offs on the high-end, and better performance on the low-cost end of
the respective product portfolios.
"As part of the Vivado Design Suite Early Access Program, we are pleased to see
Xilinx bringing ASIC class tools to the FPGA industry," said Luc Burgun, CEO,
President and Founder of EVE. "With its advanced place and route algorithms and
sophisticated design analysis environment, the Vivado Design Suite has
significantly improved our productivity and has given us a time-to-market
advantage."
Vivado Design Suite Accelerates Implementation from C With the general release of
the Vivado Design Suite, Xilinx continues its leadership in Electronic
System-Level (ESL) design by releasing Vivado High-Level Synthesis (HLS) for All
Programmable 7 series FPGA and Zynq(TM)-7000 EPP SoC devices. Vivado HLS will be
included at no additional cost to ISE Design Suite DSP Edition and System Edition
customers currently in warranty. Designers can quickly explore implementation
architectures for complex algorithms by synthesizing their C, C++ or System C
code to RTL. Vivado HLS also integrates with the System Generator tool by
creating fast simulation models for enabling the rapid development of
applications such as video, imaging, RADAR and baseband radios. Not only does
Vivado HLS accelerate algorithm implementation, it also reduces verification time
by up to 10,000x while improving system performance by enabling RTL
micro-architecture exploration.
"In FPGA design, we always use C to quickly build a system-level model for
validation of key algorithms and architectures, but we've always encountered the
problem of how we could quickly and efficiently convert C into a hardware
description language," said Hengqi Liu, Central R&D Data Center CTO at ZTE China.
"With Xilinx Vivado High-Level Synthesis, this problem has been effectively
addressed, as we recently used C to implement a key algorithm, and then used the
tool to successfully map the C code into Verilog. We verified both the
functionality and performance in Xilinx devices and the results showed that
Vivado High-Level Synthesis is very useful in an FPGA design flow."
Integration and the Xilinx Alliance Program To further accelerate designer
productivity, Xilinx continues its on-going collaboration with its growing base
of key Xilinx Alliance Program members by ensuring IP cores are validated and
design tools are available to augment the ISE Design Suite and Vivado Design
Suite tools. This collaboration is also key for the second phase of the Vivado
Design Suite rollout that includes the Vivado IP Integrator, an interactive
design and verification environment, and the Vivado IP Packager, which enables
Xilinx, third-party IP providers and end customers to package a core, module or
completed design with all constraints, test benches and documentation.
Availability In warranty ISE Design Suite Logic Edition and Embedded Edition
customers will receive the new Vivado Design Suite Edition, and those with ISE
Design Suite DSP and System Edition will receive the new Vivado Design Suite
System Edition at no additional cost.
The new features and methodologies for accelerating time to integration will be
available early next year as part of the second phase of the Vivado Design Suite
rollout. Please visit Xilinx.com to download the latest version of the ISE Design
Suite and Vivado Design Suite. Customers can also sign up for Vivado Design Suite
training classes.
About XilinxXilinx is the world's leading provider of All Programmable devices,
SoCs and 3D ICs. These industry-leading devices are coupled with a
next-generation design environment and IP to serve a broad range of customer
needs, from programmable logic to programmable systems integration. For more
information, visit xilinx.com.
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Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, Vivado and
other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their
respective owners.
XilinxBruce Fienberg408-879-4631 Bruce.Fienberg@xilinx.com |
