Optical lithography & roadmap. Full text of link posted earlier today. See the bold text................
A service of Semiconductor Business News, CMP Media Inc.
Story posted at midnight EST, 12/1/97 (9 p.m. PST, 11/30/97)
1997 SIA roadmap sets new course
for microprocessors and DRAMs
By J. Robert Lineback
SAN JOSE -- Slide over DRAM, the microprocessor has become a
designated co-driver of solid-state technology for the next 14 years,
according to the updated U.S. industry roadmap from the Semiconductor
Industry Association here.
For the first time in history, microprocessors and dynamic random-access
memories are pushing separate but equally important aspects of chip
technology, according to new SIA roadmap, which becomes available to the
public on Dec. 8.
The 196-page document targets key semiconductor milestones for the next
six generations of chip technologies, from 1997 to 2012 (see summary of the
SIA roadmap).
Officially called the National Technology Roadmap for Semiconductors,
SIA forecast is based on input from U.S. chip makers, Sematech and other
industry research groups, which have collectively concluded that the
microprocessor is best suited to push IC performance with minimum
transistor feature sizes. DRAMs remain the best vehicle to drive
device-packaging densities on chip, according to the roadmap.
Both DRAMs and MPUs are now essential to continue historical technology
trends that have doubled performance of silicon ICs every 18 months
without increasing the cost to system makers, said Jim Glaze, vice president
of technology programs for the SIA.
The new forecast updates the SIA's 1994 roadmap, identifying a range of
new technical targets for IC specifications and manufacturing processes
needed to keep the chip industry on its historical chip performance/pricing
curve, known as Moore's Law (based on observations by Intel Corp.
chairman emeritus Gordon Moore nearly 30 years ago).
Draft versions of the 1997 SIA roadmap have been floating around the
industry for more than nine months, and the finished forecast contains no big
surprises. But the completed document does map diverging courses for
DRAMs and microprocessors over the next 14 years, and it shows the U.S.
chip industry blowing past previous set targets a couple of years ahead of
schedule.
"During the development of this roadmap, it became obvious to us that logic
technology no longer followed on the back of the DRAM's needs," said
Owen P. Williams, chairman of the SIA Roadmap Coordinating Group who
is also vice president and director of external R&D for Motorola Inc.'s
Semiconductor Products Sector. "In this roadmap, we have paid a lot of
attention to the specific needs for logic devices, which are now pushing the
performance arena on chip and multi-layer metal structures."
DRAMs continue to push the density requirements of ICs, Williams said.
Until now, DRAMs were recognized as the prime technology driver for the
entire semiconductor industry.
Consequentially, the 1997 SIA roadmap measures future technology
generations in two different ways: isolate lines (or gate lengths of transitors)
for microprocessors; and dense lines (half-pitch spacings) in DRAMs. The
Leading-edge DRAM processes will move from 0.25-micron half-pitch line
densities in 1997 to 0.18 micron in 1999, according to the new roadmap,
while MPU gate lengths will go from 0.20 micron this year to 0.14 micron in
1999.
By 2012, 256-Gbit DRAMs will have 0.05-micron half-pitch line spacing,
while leading-edge MPUs with 1.4 billion transistors on a chip will be
fabricated with 0.035-micron gate lengths (see summary of the SIA
roadmap).
Several paths are also charted by the new roadmap for logic IC
milestones--depending on whether the chips are designed for high-volume,
more cost-sensitive applications or low-volume, high-performance ASICs.
For example, the roadmap sets targets for a range of usable power supply
voltages in ICs because of the disparate requirements of battery-powered
handheld applications vs. other types of end equipment.
As the SIA collected input from companies earlier this year for the new
forecast, it had hinted that the pace of developments had accelerated to the
point where the industry was introducing next-generation technology every
two years instead of the traditional three-year cycle (see story on
acceleration of roadmap targets from SBN's July monthly publication.
The U.S. trade group also had concluded that the 0.18-micron process
generation was going to emerge in 1999 instead of 2001 as was predicted in
the 1994 roadmap because 248-nanometer lithography was capable of
reaching next-generation 0.18-micron feature sizes.
In the final version of the 1997 roadmap, the SIA predicts that optical
lithography will carry the chip industry to the 0.13-micron generation in
2003. It now anticipates that non-optical exposure technologies could
become viable contenders at 0.10 micron in 2006. At that point, the
roadmap switches back to a traditional three-year technology generation
cycle, reflecting anticipated difficulties that could slow the pace of
advancements.
The following key trends are forecast to occur between 1997 and 2012,
according to the new roadmap.
DRAM die will continue to increase in size well into the next decade and
will end up greatly exceeding the chip area of microprocessors. To remain
competitive, DRAM makers will have to reduce their die size by 50% within
three years after the introduction of a new generation. This shrink will need
to be followed by another 35% reduction within the next three years.
In 2009 or thereabouts, the industry will again face the task of migrating
to a larger wafer size, moving from the just-now emerging 300-mm size to a
450-mm diameter.
Lithography exposure field sizes will steadily increase from the new
25-by-32 mm step-and-scan exposure tools to 25-by-52 mm in 2012.
An on-chip speed gap is expected to emerge and widen as it becomes
more difficult to maintain interconnect speed across the die. Transistors will
be operating at 10-GHz in 2012, but across-chip speeds will be only reach
3-GHz. Copper metal and low-k insulators are expected to help ease this
problem.
Disparate needs in battery-powered, handheld systems and other
applications will result in a range of usable power supply voltages, moving
from 1.8-to-2.5 V in 1997 to 0.5-to-0.6 V in 2012.
Costs-per-bit in DRAMs will decline an average rate of 29% a year,
according to the roadmap, to limit the rise in average-selling-prices to 41%
per new generation. To be competitive, the cost per transistor in MPUs will
have to drop 24% from generation to generation and an annual 45% decline
each year within a generation.
The maximum number of pins or balls on an IC package is expected to
grow from today's 600 to 2,700 by 2012 for microprocessors and from
1,100 to 5,500 for ASICs. The SIA roadmap also expects test costs to
continue to be $3-per-pin for cost-sensitive, performance-driven logic and
$10-per-pin for high-performance ASICs. |
