To All: Comment from Kipp Bedard of Micron.
I messaged Kipp Bedard of Micron with questions specifically about 64 meg DRAM and the cost of production. Here is my message and his response, which he has graciously allowed me to share with everyone. I hope this post will generate discussions from bulls and bears alike.
QUESTION:
"As you are very well aware, critics charge that your company is behind in technology, and the ammunition they use is the fact that you are still ramping up production of 16Mbit DRAM, when some of your competitors in Asia are starting to build 64Mbit, or even 256Mbit plants. In the most recent 10Q, there is a statement to the effect that Micron does not have the resources to spend on technological advancements. The questions no one has addressed though, is whether it will be cheaper to build one 64Mbit chip than four 16Mbit chips. This of course boils down to die size and yield. In your opinion, with the current state of the art technology, is there any cost advantage to 64Mbit chips? My understanding is that the designs of 4Mbit and 16Mbit parts are similar enough so that few modifications need to be made to ramp up 16Mbit production. However, the 64Mbit DRAM is far more complex and the learning curve will be much steeper. If this is the case, is it wiser to spend the time and money on developing 0.25 micron process, 300mm wafers etc.? When the Asian 64Mbit lines begin production, will they impact upon the pricing of 16Mbit parts? It may be wise to let the likes of Fujitsu, Samsung, Hyundai etc. pioneer so that we can learn from their mistakes and be more efficient (like the Japanese have always done in just about everything else.)
Is there any advantage to using 16Mbit chips to build 16MB SIMMS instead of 4Mbit chips? What is the largest SIMM or DIMM that you can build with 16Mbit chips? Your answer will be most appreciated."
ANSWER FROM KIPP:
"Ok, you have several questions here and I will try to answer each one.
Every time we go into a down cycle manufacturers say they are going to
switch to the "next" generation. As you already realize, the cost per bit
is what is critical (made up of operating costs, die size, mask count and
yield) to determining when the conversion will occurr. If the industry could
make 16 megs on .25 micron process we all would and they would be even cheaper
than making 64 megs on .25 micron process(fewer mask steps, smaller die size,
less silicon area lost per defect, etc.) The only additional cost to making
more 16 megs is packaging and testing the additional units which are smaller
costs then the ones mentioned above.
As an example of how we as suppliers drive the conversion (not!): experts
were claiming 3.5 years ago that the 16 meg was going to take over from
the 4 meg that year. Do you realize that it won't be until the 4th calender
quarter of 1996 that more 16 meg units will be shipped than 4 megs
for the industry?! Since the industry primarily ships dram units on simms
and soon becoming dimms, computer manufacturers don't have to redesign
mother brds to accept new memory densities. If they have designed their
mother brd correctly, they are able to accept the next density simm and
they will when the cost per bit is equal.
The laptop market and the workstation market are usually the first
industry segments to convert to the next higher density. In both cases
they do this because they gain something....in the case of the laptop, they
save on some power comsumption and they save space. In the case of the
workstation....they just simply need as much memory as they can get.
For the PC market, they purchase based on cost per bit only! So if you
want to sell 64 megs into the pc/computing/peripherals market (which
happens to make up 65-70% of all drams consumed) you have to sell the
64 meg at the same price per bit as the 16 or 4 meg dram (don't forget
our prior mask step, die size discussion).
This leads us into the discussion of simms and dimms. You can put
8, 300 mil packaged parts on each side of a simm or dimm for a total
of 16 chips. Using 4 meg dram that means you can make 8 megabyte
modules and using 16's you could get up to 32 megabytes per module. Most
PC's come with 4 slots that accept modules so that means using 4 meg drams
you can ship up to 32 megabytes of memory per box and using 16 meg drams
you can ship up to 128 megabytes per box. The last time I checked the
PC industry is averaging around 18-20 megabytes per box and on its
way to 32 meg per box. You can see how even the 4 meg will be in use
in the PC world until they move beyond 32 megabytes and the 16 could be used
until the PC world move beyound 128 megs per box.
There is a technical reason why the 64 meg can not be used in PCs very
easily. It is hard to describe in an e-mail so feel free to call if you
would like to.
It amazes me that people think we don't have technology. I ask them
to find a producer who had a higher margin on drams and a better ROE than
we did during the 4 meg cycle and the 1 meg cycle and who lost less money
than we did during the last down cycle? We have one of the smallest die
sizes and the lowest number of mask steps of any competitor. Samsung is
doing a road show to raise money and recently commented to an institutional
invester that their 16 meg has 18-20 mask steps. Our 16 meg currently has
14 and will be moving to 13 over the next year. At between $70-100 per
mask step that is a significant difference in cost per wafer. By the way,
if anyone thinks that we are not working on 64, 256 and 1 gig technology today
they are missing the boat. The only difference between all of us as
manufacturers is that some like to talk about it and some (us) don't.
We see no benefit in telling our competitors where we are in development of
new technologies."
I hope some of you will find this enlightening, as I did.
Adrian |
