IBM builds graphene chip that’s 10,000 times faster, using standard CMOS processes
By Sebastian Anthony on January 30, 2014 at 9:28 am
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Engineers at IBM Research have built the world’s most advanced graphene-based chip, with performance that’s 10,000 times better than previous graphene ICs. The key to the breakthrough is a new manufacturing technique that allows the graphene to be deposited on the chip without it being damaged (something that has heretofore been very hard to achieve). Perhaps more importantly, though, this new method is actually compatible with standard silicon CMOS processes. In short, we are closer than ever before to realizing a commercial graphene computer chip.
As luck would have it, I actually got to hold a wafer of these graphene chips when I visited IBM Research in December. That’s my hand in the photo up there, and the shot below of a graphene wafer being tested was taken by me. I also got to see the machines and tools that IBM uses to create bulk graphene, and the CMOS fab where the underlying silicon wafers are produced. In short, I am rather uniquely positioned to tell you all about IBM’s graphene chip — including the stuff that isn’t mentioned in the press release.
 How IBM Research built a graphene integrated circuit
What IBM Research has built is a silicon chip, on a standard 200mm silicon wafer, using a standard CMOS fabrication process. This chip, which is a radio frequency (RF) receiver, is just a normal chip, with resistors, capacitors, and transistors — except for one bit: the transistor channels are made of graphene. The chip’s function is very rudimentary: It receives and restores wireless signals in the 4.3GHz range.
What’s the breakthrough, then? Basically, previous attempts at building GFETs (graphene field-effect transistors) have used standard BEOL (back end of line) processes, where the active components (the transistor and its graphene channel) are built on the wafer first, and then the rest of the passive components (capacitors, resistors) and interconnects are added. The problem is, due to graphene’s weak adhesion and fragile single-atom-thick composition, this process damages the GFETs. To get around this, IBM builds the passive components first, and then only deposits a layer of graphene right at the end, to complete the fabrication of the transistors. It’s a relatively simple change, but it works rather well. [Research paper: doi:10.1038/ncomms4086 - "Graphene radio frequency receiver integrated circuit"]
 A wafer of graphene chips, being tested at IBM Research
In case you were wondering, the graphene is grown in a furnace. A copper foil is placed in a furnace at 1,050C (1,922F) with an atmosphere of methane, resulting in a single layer of graphene being deposited on the foil. The copper is dissolved away in a bath, leaving a layer of graphene floating there. The silicon wafer, with all the passive components already in place, is then used to “scoop up” the graphene layer out of the bath. (Bear in mind that the graphene is transparent, too.) This is currently the easiest way to grow large amounts of graphene, but the IBM engineers told me that the quality of graphene grown in this way isn’t great, and that having to destroy the copper substrate is expensive and inefficient.
Moving forward, it’s important to note that we’re still very much talking about ananalog chip. IBM Research still hasn’t found a way of giving graphene the all-important bandgap that is required for the fabrication of digital logic, and thus graphene-based computer processors. For next-gen processors, IBM seems to be focused on carbon nanotubes, which can have a band gap, over graphene. (More on that later, when I write up my trip to IBM Research.) Assuming we can one day create large quantities of high-quality graphene, though, there are plenty of radio and optical applications that could benefit — in theory, graphene is capable of operating at frequencies as high as 500GHz, well beyond any other material currently used in RF applications. |
