Tulvio, two quick points:
1. You wrote <<the question you pose -... whether the reduction in the line width could help to reduce the number of runs needed to finish the chip?-- is indeed the central question. I have to believe that the answer has to be affirmative, otherwise why bother with 0.25 nm.>>
- I think that since smaller line width allows higher circuit density, the chips with the same number of circuits could be made smaller, meaning more chips per wafer, lower cost per chip /higher productivity - even if the number of layers on the chip stays the same.
2. I hope you have seen posts by James Word answering my questions - he really understands lithography. James thinks that for the near future, typical arrangement could be mix and match, with i-line/DUV ratio of 4:1 to 6:1 (unless I misunderstood - still waiting for confirmation).
I don't think this neccessarily means that companies will buy new equipment in this proportion, but cost considerations are always important, especially for cash-strapped DRAM manufacturers.
If tools are ordered in 4:1-6:1 i/line to DUV proportion, CYMER may run into trouble. I'd looked at Nikon web page and found that they'd shipped 1000 steppers/scanners in 21 months (march 95-dec 96), presumably not a very good period for the semi industry. This is about 50 tools/month, 600 tools/year. Assuming that Nikon ships 600 tools in '98, their plan to sell 200 DUV tools requires manufacturers to order new equipment with 2:1 i-line to DUV ratio.
Hopefully, with DUV technology available, manufacturers will take advantage of it and start designing chips that either smaller or more powerful and thus require higher DUV/i-line ratio...
Any comments?
Regards,
Y.
|
