Robert,
You make some good points about the quality of Intel process technology. I do take issue with several of your statements however:
>>Intel's proposed integration solution is to add graphics/audio/etc.
>>into the chipset rather than onto the CPU die.
>In the long run it does not result in faster systems, and it is not
>cheaper.
There are a number of reasons why I expect that graphics/audio integrated into the chipset will produce cheaper and faster systems. Not all are obvious so I will elaborate here.
Cost:
1. CPU's are manufactured in leading edge processes, which are more expensive because of the costs associated with bringing up a new technology/fab. It is necessary to use an expensive process because of the high clock speed requirements for a competitive product.
On the other hand, chipsets use second or third generation processes because of the lower clock speed requirements of PCI/ISA/IDE/etc. As a result, the cost per transistor is much lower in the chipset than in the CPU. (i.e. you can build the same 3-D graphics unit in the chipset substantially cheaper than you can build it in the CPU.)
2. If you take a large CPU die and increase the size more, you further decrease your yield percentages. A large die has a lower percentage probability of being defect free than a smaller die.
3. A large die causes a large amount of wasted space around the edge of a circular wafer. Try filling a circle with large squares, then repeat the exercise with small squares. My point will become obvious.
4. Time to market is increased because of the additional complexity in a larger CPU. More debug/verification/speed-work is required. By putting the integration into the chipset the tasks mentioned above can be done in parallel with the CPU.
Performance:
1. Increasing the die size of the CPU impacts clock speed. Floor planning and routing become less efficient. Clock skews increase. The pad ring requires longer routes. All global wiring potentially requires longer routes. Power consumption is increased. All of these factors cause the CPU to run at a lower clock speed.
2. 3-D graphics/audio/modem/etc do not require 200-300MHZ clock speeds. The fastest 3-D graphics cards run off a 33MHz PCI bus. 3-D graphics performance is ultimately limited by memory bandwidth, not clock speed. A well designed PCI graphics chip with a next generation RAMBUS port to the frame buffer will be blazingly fast.
>(IBM ME could be the primary reason why our Cyrx investment turned
>out so poorly. The costs for production, the obstructionist
>elements, and the inability of IBM Corporate to really commit to the
>superior M1 design resulted in Cyrix being to market too late, with
>too big a die, and too little marketing and sales support. IBM
>extracted an incredibly lucrative deal from Cyrix re chips. It was
>painful, but IBM could have been the necessary stepping stone for
>visability and a market beachhead. Cyrix took that risk perhaps
>naively hoping that IBM was serious about being a partner. And Cyrix
>gave IBM a big stake, lots of chips, accesss to the technology, and
>essentially an open door to any depth of partnership IBM would want.
>What did IBM do? It took the chips and undersold Cyrx on the third
>market, for pennies profit. They didn't have the forsight, even if
>they had the means of production, to take the M1, M2, Gx, MXi etc
>and reassert a challenge to INTC for control of the hardware
>platform. Annals of Corporate Cowadice and Stupidity take note. This
>is the next useful Harvard Business School case study. IBM was a
>GREAT partner! Thanks IBM. May your stock die a thousand deaths.)
Blaming IBM is always fun but rather pointless.
>IDTI does have an interesting approach to MPU design. The simplier
>the better. Sacrifice some of the features that cost huge overhead,
>simplify the pipelining and branch prediction for smaller die size
>and faster throughput, and you are likely to wind-up with an
>equivalent speed CPU in the long run. Interesting approach. We will
>see if they can maintain competitive products. There mhz rating
>means nothing BTW. Putting instructions through a couple of segments
>versus a number of segments at the same clock speed is not the same.
>There are lots of other factors here that translate into real
>performance.
If you look at the actual benchmark numbers for C6 you will see that they are quite good for integer and somewhat low for floating point (sound familiar?)
tomshardware.com
My understanding is that the next rev of C6 will have a lower CPI (clocks per instruction) and a substantially higher clock speed.
>As far as someone buying them out, they would have to buy IDTI, a
>much bigger fish to swallow, unless IDTI wants to spin off their
>little R&D Centaur.
Based on IDTI's current stock price, we could probably get a few guys together and buy the company ourselves. You in Fuchi?
Scumbria |
