Robert,
>The generalization you are making about die size and clock speed
>does not hold true.
>I'll leave it up to you to determine what the causes for this
>discrepancy are. I'd start with the process technologies being used
>to manufacture the respective chips.
OK-
The clock frequency is largely a function of the following parameters:
1. Maximum number of gates between latches.
a. Chip architecture (common for all X86 vendors)
b. Chip microarchitecture (pipeline depth, parallelism, and
anything else which sets the different processors apart.)
c. Amount and quality of speed analysis/enhancement that has
been done by the design team.
2. Worst case switching speeds of the transistors.
a. Process technology.
b. Voltage.
c. Loading.
d. Temperature.
3. RC delays along the critical path.
a. Wire length.
b. Wire width.
c. Transistor drive strength.
d. Gate input capacitances.
Quite a few of these are controlled directly by the design team: 1b, 1c,2c,3a,3b.
Others are influenced by the quality of manufacturing available: 2a, 2b,2c,2d,3a,3b,3c,3d.
3a is largely influenced by die size.
1a is largely under the control of architectural committees.
Improvement of many of these parameters just requires hard work, time, and resources. Intel has abundant resources for attacking these issues.
There are many factors which control the clock speed of a chip. No designer likes to be encumbered by microarchitectural excesses that detract from clock speed and add to die size.
"Computer Architecture a Quantitative Approach" by Henessey and Patterson, Morgan Kauffman Publishers, is an excellent text describing the price/performance tradeoffs in microprocessor design.
Scumbria |
