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To: Curlton Latts who wrote (11634)	12/17/1997 3:53:00 PM
From: Curlton Latts	Read Replies (2) of 25960

NEC also announced plans to spend 400 billion yen to establish a production line for system-on-chip devices and a 64-megabit DRAM shrink version applying 0.25-micron geometry/200 mm wafer between 1997 and 1999. Toshiba plans to build a new mixed flow line for production of both 64-megabit DRAMs and system LSI embedded 32 bit microprocessors 3D graphic accelerators, etc., in one chip with 0.25-micron geometry/200 mm wafers, spending 100 billion yen at the Oita factory. Fujitsu will start to construct a mixed flow line with 0.25-micron/200 mm wafers for system LSI production in the Aizu factory. Many other Japanese IC manufacturers have taken aggressive steps to have their own production facilities for system LSI. Therefore manufacturers are taking the approach of embedding memory and logic in one chip, applying 0.25-micron geometry and advancing to 0.18 and 0.15 micron to realize easy production of system LSI, similar to the current production of DRAM or logic itself, even if system LSI has both structures and complex layers. semi.org Courtesy of Justa Werkenstiff on Buy when Blood In Street thread. Good Luck To Each And All Curly ~~~~~~~^^ [6.6] ....> [_]

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