The motherboard is not going to become a simple backplane,
correct. There are a lot of high speed sophisticated busses on it. Namely Memory, AGP, PCI, 1394 etc.
As for the yield improvements...
The regular Pentium Pro has 2 die within the chip package. One
is the CPU and the other is the L2 cache. They are connected
together with tiny bonding wires in a sealed PGA (Pin Grid Array) package.
If the L2 fails final test once it's in the package, they can't replace it or salvage what may be a good working CPU section so
they have to throw out the whole thing out.
With PII, they just slap the CPU die into one BGA (Ball Grid Array) and implement L2 cache externally with off the shelf components
from Hitachi, TI, etc. onto the SEC (Single Edge connector) daughtercard and route PCB traces from Processor to cache.
The processor to cache bus is called the Backside bus. It's
a high speed bus the the rest of the system has no access to,
only the Processor. By utilizing high speed PCB traces, they
can get the same speed/performance as when the CPU/L2 was one
unit in the Pentium Pro.
Also, there are thermal and density considerations when trying
to go above 512k for L2 cache within a single PGA/BGA.
This integration proved to be a very un-scaleable solution.
MEATHEAD |
