POET’S Near Term Solution
POET technology would allow the implementation of an optical interface as a single chip to
connect existing CMOS processors. The optical interface chip would integrate the laser,
modulator, modulator driver, detector, receiver amplifiers, SERDES, CDR and PLL circuits
monolithically. Both the DSP and the POET chip would be mounted face down in close
proximity on a Si carrier that forms a single common plane. The carrier has a standard MT
connector for a 12 channel fiber ribbon cable for optical I/O. The POET chip would connect to
the fibers through a proprietary, (patented) mating technique. POET also connects to transmission
lines (T/L's) on the Si carrier through standard solder bumps. The CMOS processor connects to
the same T/L's with solder bumps. The assembly cost would be reduced substantially along with
the power dissipation. The sizeable speed advantage of strained InGaAs quantum wells increases
the bandwidth. Assigning one optical interface to each processor, processors on multiple carriers
are connected optically by fiber. Alternately, waveguide patterns on the same Si carrier may
connect one optical interface to the next, enabling multiple processors on the same Si carrier to be
connected. The processor plus optical interface is the unit installed on a common PCB. With
minimum feature sizes of 0.5µm, the transmitter power at 15Gb/s is estimated to be 4mW
(0.27pJ/bit) delivering an optical power of 1mW in a chip area of 1.5x10-4mm2.
Correspondingly, the receiver power at 15Gb/s is estimated to be 6.3mW (0.42pJ/bit) receiving an
optical power of 20µW in a chip area of 1.6x10-4mm2. Upon completion, the initial solution
addresses the OE Interface requirements for both the military and commercial markets.
POET’S Longer Term Solution
POET would implement the processor by replacing all the CMOS gates with CHFET gates. The
POET processor would provide its own optical output and also performs the optical receive
function so the need for a separate interface chip would no longer be required. In addition, the Si
carrier would no longer be needed if the PCB was constructed with polymer waveguides which
then would couple to the POET output waveguides using the same proprietary, (patented)
interface technique as above. The polymer guides also connect to optical fiber I/O at a MT fiber
ribbon cable connector at the PCB edge by using polymer coating and patterning in conjunction
with pre-installed Si connector parts. At the board level, multiple processors on the same board
are connected by waveguide to transport all high speed signals while standard PCB metal lines
handle all lower speed signals. Not only would the cost of packaging this device be substantially
reduced, but also would its size, weight and power consumption while the data rate continues to
expand to the limits of the device performance. These metrics continue to improve with scaling of
feature size from the near term values stated above towards the 40-nm node since the transmitter
and receiver are directly linked to a device size rather than a circuit. Upon completion of a fully
functioning optical VLSI circuit, POET would successfully address multiple high speed markets
most notably the high speed processors and SoCs with embedded memory and high end
optoelectronic switches |
