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Politics : Formerly About Advanced Micro Devices
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To: FJB who wrote (26961)12/19/1997 1:58:00 PM
From: Investor A  Read Replies (1) of 1574001
 
Bob,

Actually, Intel has demo the PII cacheless chipset with SLAT 1(?) in the last Taipei Computer Show two weeks ago.

Intel is going to use .25u for the most profitable higher clock speed versions. The cacheless PII-266 should use the current .35u to squeeze the last milk from their current fab plants.

This technology loser could only play the game of with or w/o L2 cache to meet the challenges from AMD and Cyrix. They couldn't even fix their FPU bugs in EIGHT months after DAN411 was disclosed. There is no reasons to expect surprises from Intel, especially in technology innovations.
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