I was there for the only double header I ever attended. We didn't have much money and had a real old car. It must have cost my dad a bundle, taking four boys. We had some sandwiches but needed hotdogs too!
Nothing like the cost of games today. Somehow they lost track of poor kids today. We used to hang around the railing near the dug out and try to get the players attention. We all always had our mitts and were ready foul balls. lol I never got one. It was the most remarkable experience. Until today I never looked it up to see if I could find that day.
Here is something like a homerun in your field,.
Intel/Micron: 3-D NAND, Taper And The IMFT Cost Advantage
Jul. 28, 2015 1:00 PM ET | 11 comments | About: Intel Corporation (INTC), MU by: Jeff Groff
Disclosure: I am/we are long INTC, MU. (More...)I wrote this article myself, and it expresses my own opinions. I am not receiving compensation for it (other than from Seeking Alpha). I have no business relationship with any company whose stock is mentioned in this article.
Summary- The Intel/Micron joint venture will soon be ramping its solution to 3D NAND.
- Both companies have said their 3D NAND solution will have cost advantages over the competition.
- The cost of 3D NAND directly depends on the ability to etch vertical features with as little taper as possible.
- Therefore, investors should take note of the vertical taper of Intel/Micron 3D NAND products compared to the competition when data becomes available.
There is much excitement around Seeking Alpha these days regarding the impending availability of a 3D NAND solution from the Intel (NASDAQ: INTC)/Micron (NASDAQ: MU) joint venture (IMFT). One reason for this excitement is that both Intel and Micron are talking openly about the cost and performance advantages of their solution vs. the solutions implemented by the other players in the field including Samsung ( OTC:SSNLF) (which is already shipping 3D NAND parts in volume).
Investors who follow 3D NAND know that one big difference between the IMFT 3D NAND solution and the solutions used by all other players including Samsung is the implementation of a floating gate approach to NAND as opposed to a charge trap approach. This may be one reason for the stated advantages of the IMFT approach and is impressive in its own right since it is widely assumed that the floating gate approach is much harder to manufacture in 3D than the charge trap approach. One reason for this is that it may require significantly more lithography steps to construct the floating gate.
However, here I don't want to talk about floating gate vs. charge trap. Here I want to talk about how the cost advantages of the IMFT 3D NAND solution is likely to be due in part to a characteristic of 3D NAND called taper and the ability of the IMFT solution to have less taper than the competition.
To understand taper, it is important to first understand that manufacturing 3D NAND involves the growth of many stacked layers of alternating conducting gate layers (e.g., polysilicon) and insulating (e.g., silicon dioxide) layers. After these layers are put down, holes are patterned and etched through these layers. Deposition of several additional layers into these etched holes will finish the memory structure and create the channels of the device. Ideally, the etched hole is a perfectly cylindrical feature but in practice the etching results in a taper where the holes have a larger diameter at the top than at the bottom (see the figure below). Another patterning and etch step is performed to carve long slits into the device to partition the memory cells. These slits also have taper (not shown in the figure below).
(click to enlarge) 
Several weeks ago I came across a paper in IEEE Transactions on Semiconductor Manufacturing by Andrew J. Walker that highlighted the cost implications taper will have on 3D NAND. Basically, even a small taper can have a very significant impact on how closely features can be spaced on each layer of the device. The illustration above highlights this point. I've drawn this illustration so that the minimum width and spacing of the channels is the same in both panels. However, the small taper (3-4 degrees) in panel two requires the top-layer spacing to be much greater. Thus, the taper limits the density of features on each layer (and consequently the number of bits that can be crammed onto the whole device). To make matters worse, the reduction in single-layer density can't be overcome simply by adding more layers to the device. In fact, Walker shows that for a given taper angle (anything above about 1 degree) and target number of bits (e.g. a 128 Gbit device) there's an optimal number of layers that minimizes die size (bit density) and thus cost. Adding more layers beyond the optimal number actually increases die size. Striving to minimize gate length (layer thickness) can only help a little. Chew on that for a minute. One can't simply add layers to reduce die size and cost unless the taper angle can be effectively minimized. And this doesn't even take into consideration the negative effects taper is likely to have on performance as the number of layers increases. Basically, taper means you have a device that has different sized features at different vertical levels through the device. This is not desirable when you are trying to build a precision device.
So what are the implications of all this? First, investors should keep an eye out for any data that gets published by the various 3D NAND manufactures or outfits like Chipworks to see if any comparative analysis of taper angle can be made between devices. All the major players have plans to push 3D NAND to higher bit densities, smaller die sizes and lower costs by increasing the number of layers. If the IMFT solution to 3D NAND ends up having significantly less taper then this will give me more confidence in their roadmap and their ability to aggressively decrease costs by increasing layer count. Secondly, pay attention to any details that emerge regarding the IMFT decision to implement the floating gate approach. As I mentioned earlier, manufacturing such a device most likely requires more lithography steps but maybe these additional steps also help IMFT mitigate taper and increase feature uniformity throughout the thickness of the device. This would be great for Intel and/or Micron investors. The IMFT device would have greater reliability by implementing the time-tested floating gate approach to NAND, higher performance by achieving more uniformity throughout the device, and lower cost by successfully controlling taper. The IMFT solution to 3D NAND would dominate the market. Time will tell. |
