LSI Logic Adds 16/32-bit TinyRISC Microprocessor for Windowsr CE Products
World's smallest microprocessor offers high performance and low power for portable consumer, communications, and computer products.
Milpitas, CA, October 27, 1997 .... LSI Logic today announced a new 16/32-bit TinyRISC microprocessor specifically targeted at low power and low cost embedded applications. The TR4102 TinyRISC processor with a total area of only 1.5-sq mm is the smallest MIPS16-RISC microprocessor ever developed for system-on-a-chip applications. The TR4102 microprocessor is Windows CE compliant and features 2.5- and 1.8-volt operation, and leading edge EJTAG-compliant SerialICET-2 on-chip debug capability.
"LSI Logic was proud to be the first to implement the MIPS16 architecture and we are equally pleased today to introduce the first 1.8-V version of the TinyRISC core in our G11T, 0.18-micron process", said Larry Chisvin, Director of Marketing for MIPS Microprocessor Products, LSI Logic. "We believe that the combination of Windows CE compliance, the EasyMACRO concept, and new TinyRISC features such as SerialICE-2, raise the bar on embedded microprocessor product features."
The TR4102 TinyRISC microprocessor is perfect for emerging applications such as digital still cameras, handheld PCs, cellular phones, message pads, digital audio broadcasting, global positioning systems, set-top boxes for Internet, satellite and cable, personal information systems, video games, video cameras, automotive PC systems, high-definition TV, data broadcasting, and many other rapidly growing complex embedded applications.
The name "TinyRISC" not only refers to its "tiny" physical die size but also to its "tiny" MIPS16 code size. Code compression gives the TinyRISC microprocessor the ability to accept both 16- and 32-bit instructions using the MIPS16 architecture. This means that the total size of the code or instructions needed for the TR4102 is about 40% less than that needed for a 32-bit processor. The direct cost saving benefit is that the system memory used to store the program code also can be cut by 40%. The TR4102 is fully binary compatible with its predecessor, the TR4101 TinyRISC microprocessor, introduced a year ago.
The TR4102 was designed from the ground up to be compatible with Microsoft's highly successful Windows CE operating system. The TR4102 TinyRISC microprocessor specifically targets current Windows CE applications, such as hand held PCs, and other emerging Windows CE-centric embedded applications. Design support for the TR4102 will also include popular real-time operating systems such as Nucleus, PSOS and VxWorks.
The TR4102 features SerialICE-2, a superset of the EJTAG industry standard MIPS solution for on-chip embedded debug. SerialICE-2 has leading-edge non-intrusive debug capabilities in addition to the normal features expected from other debug methodologies. SerialICE-2 features the standard EJTAG interface, hardware breakpoints, software breakpoints in MIPS II and MIPS16, single stepping in hardware, DMA overlay and memory overlay. In addition, a SerialICE-2 provides robust trace and complex breakpoint capabilities; these sophisticated features allow successful debug of even the most difficult problems.
To simplify system-on-a-chip design, the TR4102 introduces the EasyMACRO concept. This LSI Logic CoreWarer block provides everything the user needs to create a processor subsystem. By combining the TR4102 CPU with the most commonly used system building blocks (timer, write buffer, bus interface, cache controller, fast multiply divide, and SerialICE-2), the CoreWare product development time is reduced, system-on-a-chip design is easier, and the customer's product is introduced to the market sooner.
The TR4102 is the first microprocessor core implemented in LSI Logic's 0.18-micron, G1l 2.5/1.8-V process. As such, power dissipation is only 0.5-mW/MHz. In addition, the TR4102 processor features new operational blocks: a five-cycle, multiply-and-accumulate block for fast multiply/divide for native signal processing; an 81-MHz interface bus to connect with fast memory subsystems and clock system block to support crystal and 'canned' oscillators on the LR4102 evaluation chip (the combination of 1.8-V operation with clock control greatly reduces power dissipation); and SerialICE-2.
LSI Logic pioneered the deployment of the MIPS RISC architecture in its line of MiniRISCr and TinyRISC microprocessor(æP) cores. These microprocessors have become basic building blocks in LSI Logic's extensive CoreWare Library, and are used in a fast growing line of consumer, communications and computer equipment. Semico Research estimates that more than 19-million MIPS RISC processors were shipped in 1996, clearly ranking the MIPS architecture number one in the industry.
Designs with the TR4102 microprocessor core can begin in the first quarter of 1998, with production availability for ASIC chips using this core expected by year end 1998. Design tools to support design already include a system verification environment, the TinySIMT instruction simulator, an evaluation board (BDMR4102), C Compiler tool chain and real-time operating system(RTOS). Tool chain support includes C/C++ compilers, source level debuggers, assembler, linker, utilities and libraries. The new tools for the TR4102 are extensive and include tool chains from Cygnus, Metrowerks, Green Hills Software and Algorithmics. In addition, RTOS support for TinyRISC will include products from ATI, ISI, Wind River and others. It is expected that Microsoft will announce MIPS16 Windows CE development tool support next year.
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LSI must be in the running for the processor of Next Level's set top box. The fit is definitely there. Lets hope LSI can get the deal done!!!! |
