PCI Express is preparing to upgrade to 32G
Author: Anonymous 2017-06-08 20:14
news.watchstor.com
Copper interconnect mechanism will usher in a new historic upgrade, the first will be launched in 2019, the fifth generation of PCI Express will achieve 32 G per second transmission capacity. The PCI Special Interest Group announced the plan at the current annual meeting and said it would completely end the original fourth-generation 16 GT performance per second.
The news indicates that the current widely used computer interconnection technology will usher in significant speed - in fact, with the recent slowdown in the pace of PC market development, the level of interconnection performance has been stagnant. At the same time, CCIX, GenZ and OpenCAPI as the representative of a variety of other open interconnection program is also rising rapidly.
The fifth-generation PCIe will use 128- / 130-bit encoding to deliver up to 128 GB per second in 16 GB / s 4 channels per second. Is expected to provide high-end GPU, machine learning accelerator and Ethernet and Infiniband card to provide transmission links up to 400 Gb per second.
The members of the PCI Special Interest Group have built a set of 0.3 mains for this performance specification. It is worth mentioning that the group had previously been responsible for the fourth generation of the standard version of the final review.
The emergence of this 32 G specification is responsive to the requirements of the times, especially given that the data center is continually advancing the interconnection system to a transmission rate of 56 Gb per second.
"We are able to build a large number of PHYs based on existing standards in the industry," said Al Yanes, director of the PCI Special Interest Group. "Many of the original work results in the fourth generation specification will continue to apply, which also reduces the fifth generation "Our electronic working group has full confidence in current performance figures and schedule of progress."
Engineers have yet to determine whether the new specification will limit the coverage of the interconnect system or require a higher cost of sheet material than the FR4. But they have been certain that this new standard will be able to achieve the group over the past 25 years in the development of the specifications of the backward compatibility.
After a lazy 2010 to 2017, the PCI Special Interest Group is currently accelerating the development of the road map. (Source: PCI Special Interest Group)
Brad McCredie, a researcher at IBM, said the fifth-generation PCIe represents the industry's high-speed workforce that is trying to meet the fast I / O basis, and this is the most viable way to improve the cost of Moore's Law. The experienced microprocessor engineer is currently working on Power 9, and this processor will be the first to use the fourth generation PCIe commercial CPU later this year.
At present, the industry "is still seven years ago, the third generation of PCIe as the preferred program ... ... we need to take the direction of the fourth generation of norms.We need to use these high-performance bus to achieve the communication between the accelerators, while To achieve cost reduction. "
"I think the fourth-generation PCIe adoption in the industry is likely to reach 2019. But if the PCI Special Interest Group continues to aggressively, we will be able to embrace the fifth-generation PCIe version in 2020," he added.
McCredie declined to predict the demise of the copper interconnect mechanism. But he made it clear that the hope that the fourth generation connector can still achieve 32 GT transfer rate per second, which means that after the fifth generation of copper PCIe specification is still possible to achieve.
"All this is similar to Power 6 in 2005," he explained. "We thought it was the last generation," I explained. "However, I / O engineers made a higher demand again and again, and we pushed the performance again and again To the new level.
At the same time, McCredie pointed out that IBM is also a member of CCIX and other alternative open interconnection organizations. "We are evaluating various open additional features."
Although the 16G specification is longer than expected, many companies are already introducing their own products. Of which more than a dozen have been based on equipment for the fourth generation of PCIe specification test.
Cadence, PLDA and Synopsy have demonstrated PCIe 4.0 physical layers, controllers, switches, and other IP blocks at last year's PCI Special Interest Group Meeting. It also shows the use of PCIe 4.0 100 Gb per second Infiniband switch chip, the relevant veneer and backplane and so on.
At this year's meeting, Cadence and Synopsys will drive the fourth generation of IP to more markets, including the automotive industry. Keysight and Teledyne Lecroy will showcase fourth-generation test tools, and NEC will announce a new chip to bridge PCIe packages with Ethernet.
For its part, IBM and Mellanox and Xilinx partners plan to launch Power 9 later this year, which will support fourth-generation PCIe cards and accelerators. According to the participants' forecasts, there will be more manufacturers in the future to build all kinds of Power 9 system solutions as IBM Open Power initiative participants.
"The fourth-generation PCIe bus is fast, but it does not give us too much trouble - because our own models are fully capable of docking," McCredie said.
 PCI Express performance development process.
IBM expects the PCIe bus and its own OpenCAPI interconnect mechanism to be able to host a variety of network cards, memory cards and accelerators. Interestingly, McCredie is also quite optimistic about the development potential of Intel's 3D XPoint memory as a storage-grade memory medium, which means it is likely to be transformed into a new storage layer between DRAM and flash memory with OpenCAPI's synchronous access capability.
"I think 3D XPoint is a highly disruptive technology that is absolutely fast enough to achieve synchronous access ... but I do not agree with the DIMM slots used by 3D XPoint technology," he explains.
However, the use of 3D XPoint on OpenCAPI is still at the concept level, he explained, "the idea is only talk about it."
OpenCAPI's transmission bandwidth peak is 150 GB per second, higher than the fourth generation PCIe 128 GB per second. IBM hopes to take advantage of this advantage for its Power 9 processor to attract more partners.
In addition, IBM has also been in the development of China's electronics industry to develop partners. It has released a road map, which includes the Power 9 main design and the next three years of Power 10 design ideas.
McCredie noted that IBM's recently announced 5 nanometer nanotube transistor process paves the way for its future work. "Power 11 now has the necessary process technology to achieve it," he said. |
