James,
Re: "Doesn't Intel develop it's processes remotely, in the Valley and in Portland?"
Recently (.35um and beyond), Portland PTD has developed Intel's processes.
But, they also ramp that process up to volume as well in Portland. This
is done in a Fab of 75,000 -> 100,000 sqft, then it is transferred to
other manufacturing sites (like NM for .35um). The receiving site will
send operators, tech and engineers to learn/train in Portland (part of
"Copy Exactly").
Re: "I wonder if AMD's process problems are partly related to lithography, specifically alignment."
I don't think this is the case ... one, you could always tighten the
alignment spec in litho and take a higher rework rate at a couple of levels.
Two, the design rules that give the tighter SRAM cell are:
1) Contact spacing to a poly line
2) Contact enclosure by active area
Both of these rules are dramtically (by factor of 2X) reduced with local
interconnect. I believe that this is why AMD has smaller die size.
Re: " Am I correct that speed binning is more directly impacted by CD
control and less by alignment control?"
Yes, you are correct with this statement ... but another important factor
is the device design. One must design a device that provides high drive
current (Idsat) at low supply voltages (1.8V @ .25um). This means having
a device that can produce 600ua/um for a .22um printed gate at 1.8V. This
is NOT easy to do ... and requires a lot of process/device experience.
If you design a device that produces 600ua/um for a .24um printed gate
at 2.1V (like AMD's device), this will not produce as fast a CPU.
Make It So,
Yousef |
