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Technology Stocks : AMD:News, Press Releases and Information Only!
AMD 236.73-6.1%Jan 30 9:30 AM EST
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To: Petz who wrote (3913)1/16/1998 9:53:00 PM
From: Elmer  Read Replies (1) of 6843
 
<Then why does removing the L2 cache make the LX/BX chipsets incompatible? Please refresh me on what transactions are handled by the frontside/backside busses.>

Frankly, I don't think it does make them incompatable. I can't see why it would. All L2 cache activity is handled by the P6 on the backside bus. Snoop cycles are passed to the frontside bus, but it seems to me that L1 and L2 would look identical as far as the bus protocal is concerned, so it doesn't matter to the chipset. This is probably how AMD will add a backside bus to socket7. The processor will handle all L1 & L2 activity. The Socket7 chipset, which unlike the P6 chipset, contains a cache controller. It will think it is the L2 controller but it will really be a L3 controller.
I can't gaurantee there is no incompatability, but I can't see any at this point. Where did you hear the LX & BX were incompatable?

EP
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