> The idea that Intel will regain process leadership is laughable now.
I agree to a large extent. It sounded like their CFO George Davis was clutching at straws when he projected leadership at 5nm. Whether that is just down to optimism from seeing some progress on 10nm, good feedback from 7nm developments, or aggressive targets for 5nm, would be interesting to know. Perhaps they will try to leap ahead with the next generation high numerical aperture EUV (high-NA EUV), which promises a return to single patterning. However, that is projected for 3nm or beyond, I think.
en.wikipedia.org
Anyway, if it comes down to just money, investment and aggressiveness, I doubt TSMC will allow Intel to leap ahead. Intel will need scientific and technological breakthroughs, and those are just as likely, if not more likely, to come from TSMC and their partners.
ASML, imec set up new high-NA optics lab for EUV lithography
"Accelerated development should see next-generation tool shipped by the end of 2022."
"Current EUV tools, which offer an NA of 0.33, are now entering a production ramp at a handful of chip companies, with the first commercial devices manufactured using the technology expected to appear imminently. While that initial generation of EUV systems should be sufficient for the next few years, it is thought that the high-NA optics will be needed to scale beyond the so-called “3 nm node”. The plan is to raise the NA to 0.55, and if all goes according to plan the future generation of EUV lithography equipment should be ready to begin shipping for test runs by the end of 2022, with full-scale production a few years after."
optics.org
ASML's technology page:
High-NA
"We are developing a next-generation EUV platform with a higher numerical aperture of 0.55 (“High-NA”). This platform has a novel optics design and significantly faster stages. It will enable geometric chip scaling beyond the next decade, offering a resolution and overlay capability that is 70% better than our current EUV platform. The High-NA platform has been designed to enable multiple future nodes, starting at the 3-nanometer logic node and followed by memory nodes at similar density."
asml.com |
