MPEG-2 encoders. Sorry if this was posted already............
Matsushita and Sony plan single-chip MPEG-2 encoders
By Junko Yoshida
SAN FRANCISCO -- Sony Corp. and Matsushita Electric Industrial Co.
appear to have a jump on developing low-power, smaller die-size,
single-chip MPEG-2 encoder ICs.
Such ICs will be critical in developing such consumer products as digital
camcorders, recordable DVD players, DVD-RAM for PCs and digital
VCRs with MPEG-2 encoding capabilities.
Today's multiple-piece MPEG-2 encoder chip sets -composed of several
motion-estimation chips, DCT, variable-length coders and other glue
logics-are being reduced to a single chip, according to papers presented at
ISSCC on Thursday.
Matsushita unveiled a single-chip MPEG-2 encoder with a power
consumption as low as 0.95 W and a chip size as small as 100 mm2.
Similarly, Sony disclosed a low-cost, single-chip MPEG-2 encoder for
consumer applications, featuring a newly developed wide-search-range
motion-estimation algorithm.
The biggest challenge for MPEG-2 encoder chip designers is reducing the
huge, highly computational hardware without reducing the encoding video
quality.
Matsushita's new MPEG-2 encoding IC, although designed for the
consumer market, maintains "the same professional video encoding quality"
featured in the company's previous generation chip set for commercial
DVD encoding systems, said Eiji Miyagoshi, an engineer at Matsushita's
consumer electronics system LSI development center. The single-chip
MPEG-2 device offers maximum performance of 128 Giga operations per
second (Gops), the same level as that of the company's previous chip set.
Matsushita tackled the issue of chip-size reduction by developing a new
multitasking RISC processor, running at 81 MHz, specifically tailored for
the encoder. Matsushita's engineering team also integrated, in hard-wired
blocks, a majority of the non-motion-estimation MPEG-2 encoding
functions. Those same functions used to be handled in four parallel DSPs in
the previous MPEG-2 chip set.
Sony's approach to reducing chip size was to develop two new
motion-estimation algorithms. Eiji Ogura, assistant manager for Sony's
Media Processing Laboratories, described the reduction of
motion-estimation hardware as one of the key strategies for his team to
achieve a single-chip MPEG-2 device.
The development of two algorithms-adaptive sub-sampling and adaptive
search area control-was essential to achieve two almost contradictory
goals: expanding search area to improve picture quality, while not
increasing the hardware, Ogura explained. In fact, Sony's combined
algorithms made possible a very efficient wide-search-range motion
estimation. By running the new algorithms, Sony's new chip only requires
computation power of as little as 20 Gops to do an equivalent job as
complex as 4.5 tera operations per second (Tops), which is required if one
opted for full search block-matching algorithm.
Sony also integrated a programmable controller to control everything that's
going on inside the chip. Sony picked the same proprietary DSP core used
in its MPEG-2 audio/video decoder, running at 81 million operations per
second (Mops), to do the job.
Sony's engineering team partitioned the chip by allocating any tasks higher
than macro block layer-such as motion compensation selection and rate
control-to software. It dedicated everything lower than macro block
layer-such as DCT (discrete cosine transform) and variable-length
coder-to hard-wired blocks.
Leading MPEG chip vendors in the United States, such as C-Cube
Microelectronics and LSI Logic Corp., are also developing MPEG-2
encoders for consumer electronics devices. Neither company, however,
has demonstrated their chips yet.
In contrast, the two Japanese companies are ready to roll out their
encoders.
Matsushita will start sampling its encoder chip in June in Japan. The
sample, priced at about $200, will be manufactured using a 0.25-micron
CMOS process with four-layer metal technology.
Sony's MPEG-2 chip, manufactured using a 0.4-micron CMOS process
with triple-layer metal, will be sampled in the second quarter this year.
Sample pricing is expected to be in the $600 range. Mass production will
begin in the third quarter. Sony's encoder measures 13.7 mm x 12.4 mm,
with 1.2 W power consumption. But since it's designed to be
process-independent, the chip can be shrunk down substantially, by using a
0.25-micron process, noted Toshiyuki Ishii, manager of Sony's Media
Processing Laboratories.
Integrating audio encoding capability, further shrinking the chip size, and
possibly developing a codec for both encode and decode purposes, will be
the natural next steps not only for Sony, but for any MPEG chip vendors
worldwide, observed Ishii.
Both chips from Matsushita and Sony do encoding at MPEG-2
Main-Profile @ Main-Level, as well as MPEG-2 Simple-Profile @
Main-Level. Both companies offer variable bit-rate and constant bit-rate
features in microcode. |
