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Technology Stocks : Intel Corporation (INTC)

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To: Joseph S. Lione who wrote (47527)	2/9/1998 11:38:00 PM
From: Paul Engel	Read Replies (1) of 186894

Joseph - Re: Covington & L2 Cache The Cacheless Covington chip will be slower - memory accesses will have to occur from main memory - which will run at 66 or 100 MHz instead of the 133 MHz (assuming a 266 MHz CPU speed). This all presupposes that Intel uses the same Slot 1 interface for the Covington - in which the L2 data bus cannot be brought out to the motherboard. On the other hand, if Intel changes the packaging, the L2 cache bus could be brought out to the motherboard where an external L2 cache can be provided by the MB manufacturer. All indications are that this WILL NOT be the case for Covington - but who knows? Bear in mind - Covington is targeted for cheap systems - not high performance systems. When you cut cost, something's gotta give - and in this case it is L2 cache and speed. The Mendocino chip will address this shortcoming by incorporating L2 SRAM cache on the Deschutes chip itself - somewhere between 128K, 196K and 256K SRAM. This will not come out until late this year. Paul

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