Any thoughts on Aehr? I wonder whether Tesla is requiring burn in and stabilization of the MOSFET's at the wafer level by their suppliers.
This document describes the testing that Infineon does. They are saying it is a trade-off:
- Thin oxide layer: Gives best on resistance but can only be screened by burn-in which has some negative consequences.
- Thick oxide layer: Raises on resistance but allows for gate-voltage screening.
So basically onsemi is being aggressive trying to get the lowest on resistance and needs Aehr as a result or doesn't know any better.
infineon.com
3.2 Basic aspects of SiC MOSFET gate-oxide reliability screening
At the end of processing, gate-oxides fabricated on SiC have typically a much higher early failure probability because they exhibit higher numbers of extrinsic defects, cf. Figure 2.
To make SiC MOSFETs as reliable as their Si counterparts, the gate-oxide defect density has to be minimized during processing. Additionally, innovative screening techniques, to identify and eliminate potentially weak devices, e.g. in the electrical end test, have to be developed. The screening of weak devices in the end test is typically done by subjecting each device to a high gate-voltage stress pulse with defined amplitude and time [4] [5]. The stress pulse is designed to identify devices with critical extrinsic defects while devices without extrinsic defects or with only non-critical extrinsic defects survive. The remaining surviving, screened, population shows a significantly improved gate-oxide reliability [2].
The enabler for a fast and efficient gate-voltage screening is a much thicker bulk-oxide layer than what is typically needed to fulfill intrinsic lifetime-targets. The thicker bulk-oxide layer allows the use of screening voltages much higher than the typical device use-voltage without degradation of non-defective devices which are passing the screening test. The higher the screening voltage to the use-voltage ratio, the more efficient the electrical screening [6]. By eliminating defective devices in the end test a potential reliability issue for the customer is converted to a minor yield loss for the device manufacturer. SiC MOSFETs that pass our screening test show the same excellent level of gate-oxide reliability as Si MOSFETs or IGBTs [7].
The downside of a thicker bulk-oxide layer is a slightly higher MOS channel resistance. The MOS channel resistance is directly proportional to the gate-oxide thickness and can be a major portion of the total on-resistance, in particular, for devices of lower voltage classes that provide a comparatively small drift-zone resistance. Ultimately, high screening efficiency, and hence excellent gate-oxide reliability of SiC MOSFETs, is not entirely for free, but comes at the cost of a slightly increased on-resistance. This design trade-off between reliability and performance is inevitable, however, it is possible to take advantage of the fact that on-resistance and gate oxide reliability show a different dependence on bulk oxide thickness.
While gate oxide reliability improves exponentially with oxide thickness, the on-resistance increase is only linear. At elevated temperatures, where the drift-zone resistance is more pronounced, the performance penalty is even smaller in relative numbers. To summarize, by sacrificing just a little performance by using a thicker bulk-oxide layer leads to a strong gain in reliability. Infineon decided, from the beginning, to use a Trench based MOSFET technology. The reason for this is that trench based devices, compared to planar devices, have significantly higher channel conductivities at low electric fields across the gate oxide during on-state of a MOSFET as the penalty of a thick oxide layer.
A not very attractive alternative to gate voltage screening at high screening voltages and room temperature is the classic burn-in test. During burn-in devices are typically stressed at somewhat lower gate voltages and elevated temperatures for much longer times. This approach has several disadvantages. A burn-in is time-consuming, costly, and may cause severe drift of threshold voltage and on-resistance due to long-lasting gate stress at high bias and high temperature, which is known to trigger bias temperature instabilities [8]. |
