Digging into the yields and cost issue of the C6:
Infrastructure's February report has the following comment on IDTI;
"Currently the company is generating 300 die per 200 mm wafer (8") with 60% yields - this is expected to improve over the next few months."
If this is true, (it sounds reasonable but no details as to what fab, geometry etc. this figure is associated with were given), then this is truly fantastic news for this early in the ramp.
Here's what this roughly means in terms of cost: The die cost would be 300 die x 0.6 (yield) = 180 good die/wafer. Taking a cost per wafer of $2100 (what I was given a few weeks back) and divide the number of good die into that and you get a raw die cost of about $11.10. You need to add on the ceramic package - my guess $4, assembly and test time - my guess again $5, and you get a total manufactured and tested cost of $11+$4+$5 = $20 = WOW!
Granted my numbers may be wrong by a fair margin, I suspect by as much as another +$6 - anyone with more exact assembly, packaging, and testing knowledge, please jump in here. Still, even if a tad low, this number fits perfectly with what IDT stated last Spring. You still need to add in G&A and other costs, but at an expected ASP (from Lehman's most recent report) of $60, you get a gross mfg. margin of around 60%. That's into Intel territory folks and rocks the heck out of what AMD and Cyrix/NSM are achieving. |
