Thread,
Intel's Developers Forum/RDRAM technology
Below is a (partial) schedule of events to take place on February 17: (courtesy of Flair of the Intel thread)
Two relevant presentations:
Direct Rambus* technology will achieve 1.6 Gbyte/sec of memory bandwidth with a single channel implementation. This session will describe the architecture to reach this breakthrough performance level. Furthermore Direct Rambus memory efficiency, planned memory configurations, design tools and documentation for OEMs will be discussed.
Craig Hampel, Architecture Specialist, Rambus Inc.
Focusing on the electrical aspects of the system design, techniques required to successfully implement a Direct RDRAM main memory solution at 800 Mega Transfers per second will be presented. Topics to be covered include channel design calculations, methods to reduce crosstalk and crosstalk induced skew, pcb stackup considerations as well as impacts of connectors on channel performance.
Mike Leddige, Manager, Interconnect Modeling and Design, Platform Architecture Lab, Intel Corporation
developer.intel.com
Ibexx
PS: Please note that one of the above presentations will be given by an Intel design manager whose team has been working closely with Rambus staff.
For complete information, please refer to posts by Flair of the Intel thread. |
