Shane, stuff you posted from the LSI Logic web site:
For several years, the pace of silicon-process technology has exceeded the capabilities of EDA
tools, which has led to a so-called "design-productivity gap." System designers, for example,
couldn't create eight-million gate ASICs because there were no EDA tools available to handle
these huge designs.
this solution gives engineers tools that allow them to design multi-million gate chips.
LSI should have asked some mainframe people. For over 20 years, complete mainframe designs, including several-way multiprocessors have been simulated, each and every gate, functionally and at speed, before a single one was committed to Silicon. Not only that, but the hardware was simulated with MVS and diagnostics running against it.
Tony |
