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SOI anticipates demand from sub-1-volt designs
By David Lammers
SAN FRANCISCO -- While issues of cost and process complexity continue to dog silicon-on-insulator (SOI)technology, the challenges will be worth facing when portable products demand sub-1 -volt CMOS devices.
Some circuit designers have already taken up the SOI baton. A group at IBM Corp. is developing a high-performance microprocessor using an implanted oxide layer. Others are exploiting SOI for cellular phone and pager PLL designs with very low power consumption.
But the overall tone of a 10-member panel discussing SOI for sub-1-V applications at the recent International Solid-State Circuits Conference (ISSCC) was surprisingly reserved. After two decades of slogging through cost and technology issues, only a few tens of thousands of SOI wafers are consumed each year. SOI technology is beset with myriad questions relating to wafer cost and supply, yields, gate oxides, lithography, self heating of the
silicon, design methodology, and electrostatic discharge. Design tools and circuit libraries optimized for SOI designs are limited. And there aren't yet enough people buying portable systems that would justify the higher costs associated with SOI technology.
"At first, designers think 'Yes' about SOI," said Kristin de Meyer, a researcher at Interuniversites Microelectronics Center (IMEC; Leuven, Belgium). "But then many of them realize there are many issues, such as sensitivity to the [insulator] thickness variations. And the designers must redesign their circuits. Even at sub 1V, a lot of good work is being done [in bulk silicon] with threshold voltage variation, and so SOI may be the loser."
Product managers are "very conservative," said Ted Houston, a researcher at Texas Instruments Inc. "Before they will take a chance on a new material, a lot must be proven. It is up to the circuit designers to show that unique products can be made possible by using SOI. However, bulk silicon keeps getting better at reducing the
junction capacitance."
Just converting an existing circuit design from bulk silicon to SOI wafers would provide a relatively modest 20 percent performance improvement, Houston said. That advantage "will be considerably more with good circuit design," he said.
One design engineer who was not on the ISSCC panel said circuit designers working on IC designs for cell phones are turning to SOI for BiCMOS circuits. SOI fits well with the "bipolar centric" designs used for low-voltage chips needed in digital cell phones and PDAs, said Charles Barrett-Smith, engineering manager at Silicon Wave (San Diego).
In this approach, a relatively thick insulator film measuring 0.6- to 1.0-micron is implanted. By isolating the devices more completely, a reduction in parastics for the backside transistors is achieved for both partially depleted and fully depleted devices. "At reduced voltages, we believe SOI offers some important advantages over bulk," Barrett-Smith said. "For the large integration devices needed in the handset industry, SOI provides good performance, with a 3x power improvement."
Wafer size "doesn't matter all that much" because ICs destined for portable consumer products would have a small die size and can be made on 6-inch wafers, he added.
John Pierre Colinge, a Belgian professor, displayed a long list of SOI-based prototype circuits. They ranged from an 8,000-gate ALU that runs off a 0.5-V power supply and draws 5 nanowatts of standby current, to the 1-Gbit DRAM design proposed by Hyundai Electronics. "Everyone wants to use SOI technology for SRAM, logic and RF designs," Colinge said. "At 5, 3, or 2 V, there is not much difference" between bulk and SOI-based designs. "But at 1 V there is a very large difference."
Soitec (Grenoble, France) will open a new production line in June that employs the company's "SmartCut" technology, said president Andre Jacques Auberton-Herve. SmartCut slices and bonds two substrates to create an SOI wafer, rather than using implant technology as with Simox-type SOI wafers. The cost delta between SOI and epitaxial wafers has reached the 4x level, Auberton-Herve. It will take longer to reach that cost difference when compared with bulk silicon, he said. When processors reach complexity levels that require sub-1-V power supplies, SOI wafer production levels will go from 10,000s to millions per year, Auberton-Herve said. "Think of SOI as a silicon wafer with a bit of engineering inside," he said.
The cost reduction of SOI wafers would move more rapidly if wafer manufacturers made SOI wafers in one process, said Koichiro Masahiko, group manager of advanced circuit design at Mitsubishi Electric Corp.'s ULSI Research Center (Itami, Japan). At present, a bulk silicon wafer is manufactured with its own infrastructure and overhead, and is then passed to another manufacturing process with a separate overhead for SOI wafer production. "The industry must combine the overhead" to reduce the cost multiple of SOI wafers, Masahiko said.
Wafer cost is not a deciding factor in some applications, said Seiichiro Kawamura, director of the advanced process integration department at Fujitsu Ltd. (Tokyo). The phase-locked loop (PLL) circuits test fabricated at Fujitsu on a 0.8-micron process are "very small, only 1.67 by 2.36 mm, requiring about 650 gates," Kawamura said. "More than 450 die can be obtained from a single SOI wafer. With bulk wafers, 100-MHz operation is possible, but we can do four times that with SOI. At less than 1 V operation we can still obtain 300-MHz operation."
Issues still exist, such as gate-oxide integrity and variations in SOI wafer thickness. Additional process steps are needed to properly create the source/drain region in order to deal with low breakdown voltage problems. In addition, the lithography beam tends to bounce off of the insulation layer during lithography, which reduces yields. Overall, the 90-95 percent yields that Fujitsu nomally achieves in bulk silicon drop to 60 to 90 percent with SOI technology.
"With a 2 mm by 2 mm die size, test costs dominate, so even if the SOI wafer cost is two times or more expensive, it is not the major factor," Kawamura said. "A small die size is an important factor." |
