From Electronic News, questions posed to the Synopsys' big kahuna about design tools not keeping up with process technology:
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EN: How will Synopsys handle multi-million-gate ASICs designs? A lot of talk among the
ASIC vendors is that EDA tools aren't keeping up with the demand of large,
multi-million-gate designs, so many ASIC vendors are turning to the smaller EDA
companies which are specifically targeted at deep-submicron designs. Is Synopsys going to
be able to match the goals and needs of its customers?
Dr. de Geus: "Sure. That's obviously the objective. When you were talking about
'deep-submicron' and multi-million-gate, there are two fundamental different directions one thinks
about. One is smaller things, and that's sort of the deep-submicron, and the other is, because
they're smaller, many more of them, which is really dealing with design complexity. And so one
needs to distinguish crisply about the problems in each area.
"When you're talking about smaller things, they tend to be closer together. There has been a lot of
talk of whether you can handle things such as electron migration, where the wires slowly dissolve,
because there's too much current flowing through them, for example; or things such as crosstalk,
where there's information going from one wire to another.
"Before one resolves those issues, one needs to be able to analyze them, meaning diagnose that
they are there, which is precisely the reason we merged with EPIC, because that's what they're
most specialized in. A lot of people use their tools to find if there are issues like that. Therefore, the
thrust for EPIC will be to continue to be as close as possible to the latest silicon technology.
"To me, it's actually very exciting to see that Moore's Law keeps taking little turns. And it's been
plenty in the news, so it's nothing new, but the fact that copper, for a long time, was a metal that
you didn't want to have anywhere close to your fab, makes it interesting that it's all laid out here as,
'The new metal is going to save us.' I think it illustrates exactly what happens in high technology, in
which there's always a new angle.
"On the other hand, we have this opportunity today, which is, 'So what if you have 10 million
gates, and it takes you two years to design? You'll still only miss two Christmas seasons.' That's
not appropriate. So we have always focused on how to increase the design productivity of the
designer.
"In that area, we have most definitely seen that there are two fundamental trends: Either you design
it yourself, and you move to high levels of abstraction -- which is where synthesis originally came in
-- or you start to acquire pieces of intellectual property, and then the term 'intellectual property'
also brings up a whole realm of new opportunities. The term 'reuse' which is easily stated, is not
necessarily easily executed.
"The key focus for us as a company, has been to provide a method to move to a higher level of
abstraction, and enable reuse, and this has been a foundation of the company for the past five or
six years."
EN: Would you agree with the assessment that EDA tools are not keeping up?
Dr. de Geus: "I agree with that to the extent that, for the last 25 years, that has been a statement
that we've always wrestled with, because, at any point in time, Moore's Law is an exponential, and
therefore, you have to always keep up with that.
"I think there are inflection points; and so when people say, 'The tools are not keeping up,' I think
the broader sentiment is that methodologies have to go through fairly fundamental changes in order
to be there, including the tools, but also including the behaviors of the designers. And so when you
say, 'The tools cannot support design reuse,' you have to also say, 'Are the people doing the
reuse, ready to reuse? Are they willing? And what impact does that have on the industry?' And so
all of these things are always going on in parallel.
"Do we have plenty of challenges in the industry? Absolutely! Is that one of the reasons this is an
interesting and exciting industry? Yes. I think it's the one that enables it, and I think there is a sense
that the pendulum goes back and forth between the semiconductor fabrication as the one that one
needs to focus on, and now, I think, the focus is on EDA. Many people would say, 'That's the
reason for the golden age or the time frame of EDA starting again.' And I think, even going farther,
say that that's the differentiation that is going to come to design."
EN: The term "system on a chip" is a popular one, but a number of executives say it is not
going to happen this year. They say we are missing some of the pieces of that picture. Do
you agree?
Dr. de Geus: "I think the reality is that subsystem on a chip is what is happening today, but that's
all a matter of degree. That's the same as saying, 'We're going to get 10X on Moore's Law.' Well,
yes. Is that tomorrow that you hear? It's an ongoing evolution.
"The fact that subsystem on a chip today is interesting forces the semiconductor vendors to now
start looking at what subsystems they going to be good at, i.e., to which business segment will they
be able to provide? And they certainly have to talk the language of the subsystem customer.
"And so when you say 'system on chip,' there are three words there, and they meet in the 'on' part.
That boundary is what is changing rapidly, where the semiconductor vendor has to provide a
sufficient solution to be attractive to the system house, which really wants to put it together in as
abstract a form as possible."
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Is it just me or does this guy sound like a politician? Can't see much in the way of answers to the questions posed? |
