Maxwell, <Can someone explain to me why the timing..>
Because physically each bit of information at 100MHz
consists of raising edge (plus-minus signal skew), hold
plteau, and falling edge, and all this must be within
10ns time tick. In simplified terms, if your signal is
late by 4ns, it could be sampled wrong since the clock
is also a subject of skew, jitter, and signals also need
some time to settle down.
Digging a bit deeper, all signals at these frequencies
must be considered as propagating along transmission
lines with distributed parameters. Every vias, connector
pin, or plugged stick of SDRAM causes inhomogenuity in the
transmission line, which, in turn, causes signal reflection
etc. The reflected ("bouncing") signal can be accidently
sampled at the wrong logical level if, say, the clock gets
too early or too late.
If the number of plugged DIMMs is unknown and varies,
it is impossible to design an optimal and reliable bus
at these frequencies. That's why they are also complaining
that it is hard to provide many slots for DIMMs.
There are much more in the "black magic" of the high speed
digital design. At some point you have to believe engineers:)
Regards,
Ali |
