SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Petz who wrote (28736)2/24/1998 12:25:00 PM
From: Paul Engel  Read Replies (2) of 1572712
 
Petz - re: "increased die size increases the probability of a bad
chip EXPONENTIALLY if wafer defects or defects added during
processing are the primary problem."

You are making the erroneous assumption that all defects are random such as particles on a wafer.

Those defects exist but are generally easily recognized and solved. If that were AMD's only problem, they would have solved it 6 months ago.

Processing defects - exposed vias, bridged aluminum, contact spiking/substrate shorting, junction leakage, surface inversion - are but a few of the process related defects that can occur.

It is these defects that are aggravated by too tight of tolerances and whose incidence goes up incredibly fast with decreasing feature size.

That may explain why Intel with a larger die size has incredibly high yields and AMD has ..well.. not incredibly high yields.

Paul
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News