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Politics : Formerly About Advanced Micro Devices

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To: Petz who wrote (28736)	2/24/1998 2:31:00 PM
From: Bill Jackson	Read Replies (1) of 1572712

Petz, As I see it a rain of randomly located defects from dust or other mechanisms that scatter them randomly, if each defect breaks a die then a larger die has a greater chance of being defective. If however the flaw is tiny and will not fully cut the lines on .35 micron but will cut the lines on .25, then the .25 products will fail from them and the .35 will not. This would counter the increase in yield that going smaller would bring by having a smaller chance of hitting a 'raindrop', as it would fail to smaller drops the .35 is immune to. Then you have the flaws caused br crowding, fine line alignment etc that are analogous to the same kind of flaw in printed circuit board making. If the lines are too close they might not fully etch away. If too fine they might undercut in etching giving a high resistance line, and so on. I am not in that business, but i can see how trying to densify the layout can reach a point of diminishing returns, yield wise. If you could lay a line to within .001 micron of where you want it and with that same width tolerance you could densify to within that alignment. However the talk is of .25 micron, so I have to assume the roads and pathways are to that tolerance as trying to get closer can cause tiny overlaps and other mismatches to make defects. So the entire chip needs to be relaid out allowing a bit more space between lines here and there and all masks integrated to agree with each other, as Paul says. You might end up with 325 candidates on a wafer instead of 350, but you will get 50% of that 325 working(162+ working) instead of 20% of the 350 working(70 working) for a yield increase of more than double with a bigger die due to higher rates of successful candidates. Would this larger die run a bit slower?? If this is true why did not AMD figure this out long ago? Bill

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