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Sheldon
Subj: IMP Patent Covers Zero Threshold MOSFET IC Technology;...
Date: 98-02-25 06:33:57 EST
From: AOL News
BCC: Bigkid53
IMP Patent Covers Zero Threshold MOSFET IC Technology; Improves the Performance and Extends the Operating Life of Battery Powered Equipment
SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 25, 1998--IMP, Inc. (NASDAQ:IMPX), a leading supplier of analog and mixed-signal integrated circuits (ICs), today announced that it has been awarded a patent on a method of manufacturing ICs with near-ideal transistor characteristics.
This new approach improves the performance and efficiency of analog circuits used in low-power and battery operated equipment, such as mobile phones and portable computers.
Metal Oxide Silicon Field Effect Transistors (MOSFETs) are the fundamental transistor building block in IC devices. In an ideal world, a MOSFET would have a threshold voltage near zero volts, so that any increase in "gate" voltage would turn the device "ON".
In the real physical world of semiconductor devices, however, MOSFETs enter the "ON" state at a voltage offset known as the "threshold voltage". While this lack of "ideal" operation has existed for some time, it has never really hindered past analog IC performance since large power supply voltages, typically 5 volts and above, and special circuit design techniques were used to eliminate the problems of this non-ideal physical behavior.
The trend toward lower supply voltages, driven by the widespread use of battery-powered personal electronics, has brought the MOSFET threshold problem to the forefront, especially for analog and mixed analog-digital ICs. A reduced supply voltage together with a large MOSFET threshold voltage creates a limited dynamic range for analog input signals. The desired signal levels get smaller, but the magnitude of the noise signals remain the same. This both degrades the circuits signal-to-noise ratio as well as the operational bandwidth of the device.
IMP's new process techniques can minimize the performance degradation caused by low voltage operation by creating zero-threshold P-type MOSFETs. According to Dr. Moiz Khambaty, IMP's Vice President of Technology, "Analog and mixed-signal circuit functions can be improved by zero threshold MOSFETs as these devices have a higher transconductance, lower noise and allow for higher signal levels with less distortion. This is a production-proven technique that was used in IMP's C1210 CMOS process for manufacturing nearly ten million units of the Iomega ZIP(R) read-channel circuit."
IMP's zero-threshold FETs are most useful in linear circuitry as part of an analog or mixed-signal function. For example, when used as the differential input pair of a transconductance amplifier, the zero threshold MOSFETs allow for a wider input range. Lowering the threshold voltage effectively counteracts the dynamic range reduction and added distortion that occurs when the supply voltage is lowered from 5 volts to 3 volts. This can be crucial in minimizing bandwidth degradation due to lowered transconductance.
But zero-threshold MOSFETs have more applications than just linear amplifiers. For example, a zero-threshold FET used as an analog switch offers improved performance since the low threshold results in a lower "ON" resistance for a given gate-to-source voltage.
Zero Threshold Patent Details
The objective of zero MOSFET threshold is achieved by a unique method of implantation that involves an additional selective implant such that the selected PMOS threshold voltage is zero volts. During this additional implant, the zero-threshold NMOS channels are masked and not affected. Only selected PMOS devices are designated to have the zero threshold feature during the second ion implant step. Zero threshold PMOS devices can be created all at once or individual devices can be implanted separately.
The "native" threshold voltage is the inherent threshold voltage in MOSFET devices prior to ion implantation. The native threshold voltage for PMOS FETs ranges from -1.6 volt to -1.8 volt. After an implantation the normal PMOS FET threshold is 0.6 volt to 1.1 volt. A second implant applied to selected PMOS FETs results in substantially zero threshold devices. PMOS FET thresholds between -0.2 volt and 0.2 volt are possible. Zero threshold devices have thresholds as close to zero as possible. The native or unimplanted threshold voltage for the NMOS FETs ranges from -0.2 volt to 0.2 volt and is thus the zero threshold voltage.
Prior to this patent, zero threshold NMOS FETs could be achieved by using the "native" threshold of the devices -- the zero threshold for NMOS FETs is the "native" threshold voltage. By combining the "native" NMOS devices with the enhanced zero threshold PMOS FETs described in the patent, a complementary pair of low-threshold MOSFET devices is achieved.
Past Limitations
Although it had been known that a second implant could be used to achieve a zero threshold voltage, this technique was considered impractical because "punch-through" was an inevitable result. "Punch-through" is when the applied voltage causes the FET drain to enlarge until it contacts the FET source -- the result being a substantial leakage path that renders the FET useless. The IMP zero-threshold patent describes the method of creating zero threshold PMOS FETs that are not "soft" and do not have a high amount of source-drain leakage.
Besides describing the process steps needed to create the zero-threshold PMOS FETs, the patent also claims a number of IC configurations using NMOS FETs with zero threshold PMOS FETs in a variety of amplifier and complementary analog switch configurations.
United States Patent Number 5,493,251, was issued to Dr. Moiz Khambaty, Vice President of Technology and assigned to IMP, Inc. -0- Statements in this press release regarding IMP's business that are not historical facts are "forward-looking statements" that involve risks and uncertainties, including, but not limited to demand for the Company's products, foundry utilization, the ability of the Company to develop new products, demand by end-users of the products produced by the Company's customers, and the other risks detailed from time to time in the Company's reports filed with the Securities and Exchange Commission, including the Company's most recent Annual Report on Form 10-K and Quarterly Report on Form 10-Q. -0- IMP, Inc. designs, manufactures, and markets standard-setting analog integrated circuits and specialty analog wafer foundry processes for data communications interface and power management applications in computer, communications, and control systems world-wide. Products are manufactured on CMOS, BiCMOS, and EEPROM processes in the company's ISO 9001 qualified wafer fabrication plant in San Jose, California.
Company headquarters are located at 2830 North First Street, San Jose, California, 95134-2071. Telephone: 408/432-9100. Fax: 408/434-0335. For further information about IMP, please visit our home page at impweb.com or Email info@impinc.com. -0- Note to Editors: A photograph of Dr. Khambaty is available by calling 408/434-1467.
--30--ik/sf* bl/sf
CONTACT:
IMP Inc., San Jose
David Gillooly, 408/434-1467
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