RE:"Please explain."
Joe,
During the past decade there have been two fundamental camps in CPU design. Those that wanted to increase performance through complexity, and those that increased performance through simplicity.
Alpha was the ultimate example of a simple implementation. The architects focused on clock rate. M1 and K6 are good examples of complex implementations. Those architects focused on achieving performance by minimizing latencies in the pipeline, at the expense of megahertz, die size, power consumption and time to market.
Alpha is far and away the highest performance CPU.
It is widely recognized that the Alpha approach was far more sensible. Consumers want high megahertz, low power, low cost CPU's. Glenn Henry, the architect of C6, wrote an excellent piece addressing this concept.
winchip.com
It would make more sense for the Cayenne design team to focus on changes which increase megahertz, rather than architectural tweaks which decrease instruction latencies.
RE:"Even though MediaGX accesses memory differently, memory still runs at it's own speed (83 MHz apparently in MediaGXm), not at the speed of the CPU."
There is a lot of discussion on this thread about "bus speeds." The bus that is being referred to, is the bus which connects the CPU to the memory/IO controller (commonly known as the north bridge.) Media GX integrated this bus (and the north bridge) inside the CPU, causing it to run at CPU speeds. MXi will apparently also run this bus at CPU clock speeds.
If you believe that "bus speed" is important, you should recognize that the bus you are referring to runs at very high speed inside the Media GX product line.
On the other hand, the "SDRAM bus", which connects the memory controller to the memory, will always be limited by the speed of the SDRAM modules, regardless of "bus speed" or chipset design. |
