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From: BeenRetired10/9/2025 5:49:28 AM
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AVGO: 3nm Tomahawk 6 – Davisson shipping...sipping watts.
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Broadcom announces shipping of Tomahawk 6 – Davisson

Story by TheFly20h

Broadcom ( AVGO) is now shipping Tomahawk 6 – Davisson, the company’s third-generation Co-Packaged Optics Ethernet switch. Designed specifically for the accelerating demands of AI networking, TH6-Davisson is the industry’s first to deliver an unprecedented 102.4 terabits per second of optically enabled switching capacity. Doubling the bandwidth of any CPO switch available today, TH6-Davisson sets a new benchmark for data center performance. Built on Broadcom’s foundation of CPO innovation and field shipments, the platform doubles the bandwidth of any CPO switch available today, while delivering major advancements in power efficiency and traffic stability to unlock optical interconnect performance required to scale-up and scale-out the world’s most demanding AI clusters.

Copilot:
Yes — Broadcom’s Tomahawk 6 Ethernet switch chip is built on a 3nm CMOS process node.

Here’s how that fits into the broader context of AI networking and lithography:

Tomahawk 6 Node Details
  • Process Node: 3nm CMOS, a shrink from the 5nm node used in Tomahawk 5.
  • Architecture: Multi-die design with a central core die and configurable chiplets for either 100G or 200G PAM-4 serdes.
  • Bandwidth: Delivers 102.4 Tbps, doubling the throughput of its predecessor.
  • Power Efficiency: Consumes significantly less than 1W per 100Gbps, well below 1,000W total — a major leap from Tomahawk 5’s ~512W envelope.
Why 3nm Matters
  • EUV-Driven: 3nm nodes rely heavily on EUV lithography, especially for logic and SRAM-rich packet processing cores.
  • AI Optimization: Designed for near-100% network utilization in AI clusters, where latency and bandwidth bottlenecks are unacceptable.
  • Co-Packaged Optics (CPO): Uses TSMC’s COUPE™ photonic engine for substrate-level integration, reducing trace loss and signal conditioning overhead.
Tomahawk 6 is a prime example of how EUV-enabled 3nm logic is being deployed not just in compute, but in high-throughput networking — a critical enabler for AI scale-out. Want to map how this node choice affects mask count or inspection load per die? I can break that down next.
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