Applied Materials advances AI chip performance with hybrid bonding and e-beam metrology
Monica Chen, Hsinchu; Charlene Chen, DIGITIMES Asia
Thursday 9 October 2025
To enhance the performance of advanced logic and memory chips required for AI computing, global semiconductor equipment leader Applied Materials has unveiled new semiconductor manufacturing systems. The company announced three major products centered on developing AI chips' key areas: integrated die-to-wafer hybrid bonding systems, gate-all-around (GAA) transistor-based advanced logic processes, high-bandwidth memory (HBM) DRAM, and cutting-edge packaging technologies that optimize chip performance, power consumption, and cost.
As chip complexity continues to rise, Applied Materials is accelerating materials engineering improvements to boost efficiency and reduce power usage in response to AI's scaling demands. The company also deepens early-stage collaboration with customers to jointly develop technology roadmaps that speed up chip makers' innovation cycles.
High-end GPUs and HPC chips currently use advanced packaging architectures that integrate multiple small dies into complex systems. Emerging hybrid bonding chip stacking technology employs direct copper-to-copper bonds, significantly improving overall performance, power efficiency, and cost-effectiveness. However, as chip packaging grows more intricate, large-scale production of hybrid bonding faces challenges.
Applied Materials partnered with Besi NV to develop the Kinex Bonding system, an integrated die-to-wafer hybrid bonding solution that consolidates all critical process steps into a single platform. Compared to non-integrated approaches, this system offers multiple advantages and has already been adopted by leading logic, memory, and OSAT firms.
Meanwhile, the source and drain structures critically impact the performance and reliability of today's most advanced GAA transistors, forming the transistor channel through epitaxial (epi) deposition within deep trenches.
Traditional epi techniques struggle to fill these high aspect ratio source/drain trenches without voids or uneven growth, which can degrade device performance and reliability.
To address this challenge and maximize chip performance, Applied Materials developed the Centura Xtera Epi system featuring a unique small-volume reaction chamber design that integrates pre-clean and etch processes. This enables void-free GAA source-drain structures while reducing gas consumption by 50% compared to conventional epi methods. The Xtera system is already in use by logic and memory chipmakers.
The newly introduced PROVision 10 electron beam metrology system has been adopted by several logic and memory manufacturers to improve yields of highly complex 3D chips. Designed specifically for advanced logic devices such as GAA transistors and backside power delivery architectures, next-generation DRAM, and 3D NAND chips, it is the first metrology tool employing cold field emission (CFE) technology.
Compared to traditional thermal field emission (TFE), CFE enhances nanoscale imaging resolution by up to 50% and increases imaging speed tenfold. Its capabilities support critical process control tasks, including extreme ultraviolet (EUV) layer alignment, nanosheet measurement, and detection of epitaxial voids in GAA transistors, making it an essential inspection tool for sub-2nm advanced nodes and HBM integration. |
