Intel BSPD: -44% masks & -42% steps.
Inside Intel’s Fab 52 — the Arizona mega foundry building the future of 2nm chips---clown---They're 1.8nm---
Copilot:
Intel’s M0–M2 direct print EUV refers to the use of Extreme Ultraviolet Lithography to pattern the tightest-pitch metal layers (M0, M1, M2) directly—without multi-patterning—on its 18A process node. This enables finer interconnects, better performance, and lower power.
What Are M0–M2 Metal Layers?
- M0, M1, M2 are the lowest-level metal layers in a chip’s interconnect stack.
- They connect transistors to each other and to higher-level routing layers.
- These layers require extremely fine pitches (e.g., 30–36 nm), making them the most challenging to pattern.
What Is Direct Print EUV?
- Direct print EUV means using a single EUV exposure to pattern features—no multi-patterning like LELE or SADP.
- Intel uses this for M0–M2 layers in its 18A node, leveraging:
- Optimized EUV illumination
- Advanced photoresists
- Full-field corrections (flare, slit, black border)
- Optical Proximity Correction (OPC) tuned for tight pitches
This approach simplifies mask design, improves yield, and reduces overlay errors.
Why It Matters
- Performance: Tighter metal pitches reduce resistance and capacitance, boosting speed and lowering power.
- Design flexibility: Direct print allows more custom routing and layout freedom for chip architects.
- Manufacturing efficiency: Avoids complex multi-patterning steps, reducing cost and cycle time.
Intel’s success with direct print EUV on M0–M2 layers is a key enabler of its RibbonFET + PowerVia architecture on 18A, supporting high-density AI, CPU, and GPU integration.
Want to compare this with TSMC’s approach to metal patterning on N2 or Samsung’s gate-all-around roadmap?
PS
Client Compute is going to be extremely competitive.
I WAG yuge demand.
Ditto Fone.
ONLY the terminally stoopid don't get it. |
