EXE: "Intel’s throughput suggests aggressive early adoption"
Copilot:
Yes—Intel confirmed that its high-NA EUV machines (ASML Twinscan EXE:5000) processed 30,000 wafers in a single quarter at its D1 development fab in Oregon. This marks a major milestone in transitioning high-NA EUV from calibration to active pilot production.
What Intel Actually Reported
- Tool Deployment: Intel installed two ASML Twinscan EXE:5000 high-NA EUV systems at its D1 fab near Hillsboro, Oregon.
- Wafers Processed: In Q1 2025, Intel processed ~30,000 wafers using these tools—an unusually high volume for what ASML classifies as “pre-production” equipment.
- Process Efficiency: These high-NA tools reduced lithography from three exposures and ~40 steps to one exposure and single-digit steps, dramatically improving throughput and cost efficiency.
- Resolution Leap: Achieved 8nm resolution with a single exposure, compared to 13.5nm with low-NA EUV.
Production vs Pilot
- Not yet mass production: Intel is using these tools for pilot production and process development, not full-scale commercial output.
- Node Alignment: The wafers processed are tied to Intel’s 18A node, with high-NA EUV being tested before full deployment at 14A.
- Tool Status: ASML still classifies EXE:5000 as pre-production, but Intel’s throughput suggests aggressive early adoption.
Strategic Implication
Intel’s ability to process 30,000 wafers in a quarter with high-NA EUV tools signals:
- Tool maturity: Reliability is reportedly 2× better than prior EUV generations.
- Yield ambition: Intel is pushing to stabilize 18A yields and prepare 14A for high-volume rollout.
- Foundry credibility: This positions Intel as a serious contender in advanced logic foundry services, rivaling TSMC and Samsung.
Want to map how this affects ASML’s fab loading or Zeiss mirror throughput? We could sketch the ripple. |
