SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : ASML Holding NV
ASML 1,059-1.5%Oct 31 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
From: BeenRetired10/16/2025 8:22:06 AM
   of 42261
 
EUV intense A16 GAA SPR 2H26.

TSMC’s is its A16 first Angstrom-class process node (1.6?nm), combining GAAFET nanosheet transistors with backside power delivery (SPR) for major gains in performance, power efficiency, and density. Volume production is expected in late 2026.

Here’s a breakdown of what makes A16 a milestone in semiconductor manufacturing:

Architectural Innovations
  • GAAFET Nanosheet Transistors: A16 uses second-generation Gate-All-Around FETs, which wrap the gate entirely around the channel for superior electrostatic control. This improves drive current and reduces leakage compared to FinFETs.
  • Super Power Rail (SPR): A16 introduces backside power delivery, separating power and signal routing. This reduces IR drop, improves power integrity, and enables tighter signal routing.
Performance, Power, and Density (PPA)

Compared to TSMC’s N2P (2?nm-class):
  • Performance: +8–10% at same voltage and complexity
  • Power Efficiency: –15–20% at same performance
  • Density: +7–10% (approx. 1.07×–1.10×)




Ecosystem and Adoption
  • EDA/IP Support: Certified by Synopsys and Cadence for analog, digital, and 3D-IC/chiplet flows
  • Early Design Wins: Apple, AMD, Nvidia, and OpenAI are expected adopters for AI and compute-heavy designs
  • Tooling: Fab 21 in Arizona will support A16 alongside N2/N2P nodes
Strategic Outlook
  • No High-NA EUV Required: A16 achieves full-node scaling using existing EUV platforms, avoiding the need for costly High-NA EUV
  • Future Nodes: A14 (1.4?nm) and CFET architectures are planned successors, with potential Forksheet FET and 3D-IC integration
TSMC’s A16 marks a shift from mere dimensional scaling to architectural redesign—ideal for AI, HPC, and dense consumer SoCs. If you're tracking competitive positioning, A16’s early SPR integration and GAAFET maturity could give TSMC a lead over Samsung and Intel’s roadmap pivots.

Would you like to compare A16’s SPR implementation to Intel’s PowerVia or Samsung’s MBCFET roadmap? I can break down the routing, thermal, and yield implications.

PS
5nm a mainstay node.
EUV/ArFi Shrink n Stack bonanza JUST started.

ASML
Village...big contributor to successful ramp.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext