Beyond Moore’s Law: Scientists build world’s first six-layer hybrid microchip
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Story by Rupendra Brahambhatt• 48m
In the race to make electronics smaller, faster, and more efficient, scientists at King Abdullah University of Science and Technology (KAUST) in Saudi Arabia have achieved a breakthrough that could reshape the future of microchips.
They have built the world’s first six-stack hybrid CMOS (complementary metal-oxide semiconductor) microchip tailored for large-area electronics. Until now, hybrid chips with vertical stacking were limited to two layers.
This advance pushes integration density way beyond what was possible earlier.
“In microchip design, it is all about packing more power in less space. By refining multiple steps in the fabrication, we provide a blueprint for scaling vertically and increasing functional density far beyond today’s limits,” Saravanan Yuvaraja, lead researcher and a postdoc at KAUST, said.
According to the researchers, this is more than just a technical feat, as it points toward a new architecture for smart electronic devices, wearables, and medical devices.
The trick to going beyond two stacksFor decades, the semiconductor industry has relied on a simple rule—shrink the transistor to fit more of them on a flat surface. However, this strategy is now hitting a wall as transistors become extremely small, quantum effects and rising production costs make further miniaturization nearly impossible.
The solution, researchers believe, lies not in going smaller but in going vertical, i.e., stacking circuits layer by layer like a skyscraper, but doing so comes with serious challenges.
For instance, traditional chip-making requires high temperatures that can damage lower layers, and aligning multiple layers with perfect precision is highly difficult. Until now, these obstacles have limited how many layers can be stacked safely and effectively.
To overcome such challenges, the researchers rethought how microchips are built from the ground up. Instead of relying on high-temperature fabrication, they developed a process in which no step exceeded 302 degree Fahrenheit (150 degrees Celsius), with most of the work done close to room temperature.
This approach prevented damage to the underlying layers as new ones were added. Each layer of the chip contains tiny transistors that handle electrical signals. Some are made from inorganic materials (n-type indium oxide) and others from organic compounds.
These complementary materials, when combined in a single structure, create what’s known as a hybrid CMOS architecture, the backbone of most electronic devices. Moreover, the team also refined how each surface was prepared and connected. By keeping the interfaces smooth and precisely aligned, they ensured that electrical signals flowed efficiently between the layers.
The end result was a chip with six active layers—three times more than any hybrid CMOS built before. It demonstrated stable operation and energy-efficient logic circuits, proving that vertical stacking could deliver higher performance without overheating or electrical interference.
Promising a bright future of electronics
This new approach to chipmaking could transform a range of technologies. For flexible and wearable electronics, it could lead to more compact sensors and medical devices that can bend, stretch, or even be integrated into fabrics.
For the Internet of Things, where millions of tiny devices need to operate efficiently, vertically stacked chips could offer powerful computing with minimal power use, and for space and environmental technologies, their low weight and high performance make them ideal for satellites and remote sensors.
However, the research is still at a proof-of-concept stage. The chips must become more stable at higher temperatures and be adapted for large-scale manufacturing before they can enter the commercial market.
The KAUST team plans to refine the materials and improve the long-term reliability of their design while exploring how to integrate even more layers and functionalities in the future.
The study is published in the journal Nature Electronics. |
