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Politics : Formerly About Advanced Micro Devices
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To: StockMan who wrote (28822)2/25/1998 4:47:00 PM
From: Maxwell  Read Replies (1) of 1573134
 
Stockman:

<<For starters covington is a stop gap solution for 3 months before mendocino (which has L2 cache on chip). Also Intel has said that it would be about 10% slower, and its believable because with AGP, ultraDMA, and 266Mhz .>>

So what? Socket 7 has AGP, 100MHz bus speed, and ultraDMA, and a BIG L2 CACHE. A Castrated PII has NO DIB (dual independent bus). It relies everything on system memory which makes it slow as hell.

You need to take a course in computer architecture to understand what you are talking about. Let me give you a simple introduction.

When a CPU wants to make an execution it goes

1st To the L1 cache to look for the instruction. If it doesn't find

2nd Then a snoop is sent by the CPU to look into the L2 cache. L2
cache is an SRAM that has a response of about 2-4 ns. A SDRAM has a delay time of 10ns. Thus SRAM is 2X to 5X faster than SDRAM.

3rd If the L2 cache doesn't have it then it goes to the chipset and call up the system memory. The system memory runs at system bus speed of 66MHz-100MHz. The memory then start to transfer the data to the CPU and the L2.

Intel opt to bypass the 2nd stage which will SIGNIFICANTLY reduce the system performance. Even if INTEL improves the Castrated Covington by 2 fold the system is STILL LIMITED by how fast data can transfer from system memory to the CPU.

So get lost to the mountain to learn your basic.

Maxwell
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