Yes—Lip-Bu Tan has signaled a yearly cadence by accelerating Intel’s transition from 18A to 14A, with 14A already in development and showing better early yield and performance than 18A at the same stage.
Here’s how the cadence is shaping up:
Evidence of a Yearly Cadence Under LBT
- 18A (2025): Panther Lake is launching this year on 18A, with yields now predictable and Fab 52 fully operational.
- 14A (2026): Intel has already processed over 30,000 wafers on 14A using High-NA EUV, and early PDK milestones are ahead of where 18A was at the same point.
- 14A-P and 14A-PT variants are in the pipeline, mirroring the 18A-P/18A-PT extensions Gelsinger introduced—suggesting a rolling annual refinement model.
This mirrors Gelsinger’s “5 nodes in 4 years” tempo, but with Tan’s twist: he’s emphasizing customer co-design, yield maturity, and foundry viability over pure marketing milestones.
Strategic Implications
- Tan confirmed that 14A is being developed “on a milestone basis” with multiple customers, and that yield and reliability are already improving.
- CFO David Zinsner added that 14A is ahead of 18A at the same maturity point, suggesting a tighter, more confident ramp.
- This cadence supports yearly node evolution—not just for Intel’s internal products, but to attract foundry clients like NVIDIA, Apple, and AI startups.
Why It Matters
- High-NA EUV is already in use for 14A, reducing layer steps from 40 to under 10—cutting cycle time and cost.
- Tan’s background in EDA and venture capital suggests he’s optimizing for design enablement and ecosystem buy-in, not just transistor density.
- If 14A hits volume in 2026, it confirms a Gelsinger-like yearly cadence, but with more emphasis on execution and customer alignment.
So yes, your instinct was right: the 18A to14A handoff does indicate a yearly rhythm under Tan. Want to explore how this cadence affects ATP packaging timelines, reticle reuse, or Southeast Asia’s substrate capacity? Or how 14A’s High-NA exposure reshapes die floorplanning? I’m game |
