Just another flawed "expert" "report".
The chip landscape is changing, the "waterfall effect" is slowing down, and silicon is getting more expensive
In the context of semiconductor design, Chris Bergey, Arm's Senior VP and GM of the Client Line of Business, referred to the "waterfall effect" as a way to describe a long-standing industry practice: today's flagship chip technology eventually cascades down to tomorrow's mid-range and budget devices. Chipmakers often amortize their massive development costs by reusing last year's high-end system-on-chip (SoC) in lower-priced products or selling slightly detuned versions for cheaper devices. Of course, consumers have historically benefited from this waterfall of innovation. Advanced features like faster processors, better graphics, and new connectivity standards all eventually reach affordable gadgets as the cutting-edge moves forward.
Yet this "waterfall effect" is currently under strain, according to Bergey. In an interview, Bergey explained to us that the surging complexity and costs at the top end are widening the gap between premium and mainstream chips. The result is a potential breaking point where simply repackaging last year's silicon for cheaper devices "may not work" anymore.
Premium chips are more expensive than ever
Prices have been rising for a long time
One big reason for this increase in cost is that cutting-edge fabrication has become far more expensive. Foundries like TSMC charge much more for newer, smaller transistor nodes. Apple's A-series chips, which form the basis of Apple's M-series, are a good way to illustrate that point. Back in 2013, the Apple A7 (built on a 28nm process) was manufactured on wafers that cost about $5,000 each, whereas by 2024, the A17/A18 Pro (using a 3nm-class TSMC process) saw wafer prices around $18,000. That's a three-and-a-half-times jump in just a decade, which has seen the cost per millimetre of wafer jump dramatically.
Copilot:
You're absolutely right to challenge the logic—while 3nm wafer costs have surged, the cost per transistor and die count per wafer have also improved dramatically. The raw wafer price alone doesn’t capture the full economic picture.
Let’s unpack the nuance:
Die Count: 3nm vs 28nm on a 300mm Wafer
- Wafer area: ~70,685 mm² (for a 300mm or 12" wafer)
- Die size (approximate):
- 28nm: ~100 mm² (e.g., Apple A7)
- 3nm: ~50 mm² or smaller (e.g., Apple A17 Pro reportedly ~50–60 mm²)
Estimated dies per wafer (before yield loss):
- 28nm: ~600–700 dies
- 3nm: ~1,200–1,400 dies ? Roughly 2× more dies per wafer at 3nm vs 28nm
Yield and Throughput
- Yield: TSMC’s 3nm (N3B/N3E) reportedly achieves good yields, especially for Apple, which may pay per known good die (KGD), not per wafer.
- Throughput: EUV-based 3nm lines are more efficient per layer (fewer masks, fewer steps), even if EUV tools are expensive and slower per exposure. However, fewer multi-patterning steps means higher net throughput per fab line compared to 28nm DUV.
Transistor Density and Value per mm²
- 28nm (A7): ~1 billion transistors
- 3nm (A17/A18 Pro): ~20 billion transistors
- Transistor density: ~20× increase
- Cost per mm²: Rose from ~$0.07 (28nm) to ~$0.25 (3nm)
But cost per transistor has dropped significantly, even if the cost per mm² rose.
Bottom Line
- Wafer cost ? economic efficiency. The value per wafer (in terms of performance, transistor count, and die count) has grown faster than cost.
- Throughput and yield improvements—especially with EUV—have helped offset rising equipment and material costs.
- Apple’s per-good-die pricing and stable die sizes further optimize economics.
So yes, the logic in that quote is incomplete. It’s like saying a Ferrari costs more than a Civic without acknowledging that it laps the track 3× faster and carries more compute per cc. Want to model cost-per-transistor or per-performance-watt across nodes? I’d love to run that with you.
PS
Nvidia delivers 80% markup with 20% chip.
Dozens and dozens attacking that.
As EXE and NXE continue to ramp quite nicely.
There's ALWAYS the next Huang. |
